Prosecution Insights
Last updated: July 17, 2026
Application No. 18/424,998

SEMICONDUCTOR DEVICE WITH DUAL DOWNSET LEADFRAME AND METHOD THEREFOR

Non-Final OA
Filed
Jan 29, 2024
Examiner
LEE, WOO KYUNG
Art Unit
2815
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
NXP Semiconductors N.V.
OA Round
1 (Non-Final)
82%
Grant Probability
Favorable
1-2
OA Rounds
8m
Est. Remaining
96%
With Interview

Examiner Intelligence

Grants 82% — above average
82%
Career Allowance Rate
155 granted / 189 resolved
+14.0% vs TC avg
Moderate +14% lift
Without
With
+14.3%
Interview Lift
resolved cases with interview
Typical timeline
3y 2m
Avg Prosecution
35 currently pending
Career history
217
Total Applications
across all art units

Statute-Specific Performance

§103
84.8%
+44.8% vs TC avg
§102
8.2%
-31.8% vs TC avg
§112
7.1%
-32.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 189 resolved cases

Prosecution Timeline

Jan 29, 2024
Application Filed
Apr 28, 2026
Non-Final Rejection mailed (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12672561
DIE ATTACH SYSTEM
4y 3m to grant Granted Jun 30, 2026
Patent 12666889
METHOD FOR POROSIFYING A MATERIAL AND SEMICONDUCTOR STRUCTURE
3y 6m to grant Granted Jun 23, 2026
Patent 12666796
DISPLAY DEVICE
3y 2m to grant Granted Jun 23, 2026
Patent 12666668
SEMICONDUCTOR DEVICES WITH BONDING LAYERS
2y 11m to grant Granted Jun 23, 2026
Patent 12660295
SEMICONDUCTOR DEVICE INCLUDING THIN FILM TRANSISTOR AND METHOD FOR FORMING THE SAME
3y 5m to grant Granted Jun 16, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
82%
Grant Probability
96%
With Interview (+14.3%)
3y 2m (~8m remaining)
Median Time to Grant
Low
PTA Risk
Based on 189 resolved cases by this examiner. Grant probability derived from career allowance rate.

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