Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 2, 6-11 and 18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Akin et al. (U. S. Patent 11,525,740).
As for claim 1, Akin et al. discloses a method of estimating a junction temperature of a transistor (i.e., measuring the junction temperature of the SiC MOSFET transistor in Figs. 3, 4, 8 and multiple transistors in Fig. 25) in a power electronics converter (i.e., when used as in a power converter application, see col. 8, line 63-64 and converter application in Fig. 25) configured to convert between first and second supply voltages, the method comprising:
providing a gate switching signal to the transistor (using the gate drive circuit and the microcontroller to send the gate switching signal; see Fig. 3 and 4 and col. 6, lines 63—67);
measuring a rate of change of current through the converter during a switching period of the transistor (i.e., measuring the di/dt during switching of the transistor; see Col. 5, line 31--col. 6, line 59) and
outputting an estimated junction temperature of the transistor based on the measured rate of change of current (using the junction temperature measurement circuit and the microcontroller in Fig. 4 for outputting the junction temperature measured),
wherein the rate of change of current is measured while a gate voltage (Vgs) of the transistor is above a gate threshold voltage (see the Vg reference in Fig. 3; col. 5, lines 39-40) and a drain-source voltage (see Vds in Figs. 1, 10 and 11) across the transistor is above a predetermined fraction of the first or second supply voltage whereby the rate of change of current is measured in a linear region (i.e., the current Id is measured in a liner region during switching period as shown in Fig. 1, 10, 11).
As for claim 2, Akin et al. discloses the method of claim 1, wherein the switching period is between around 20 ns and 100 ns (i.e., between 50 ns and 100ns in Fig. 1).
As for claims 6 and 7, Akin et al. discloses the method of claim 1, comprising changing a value of a gate resistor connected to the transistor prior to providing a gate switching signal to the transistor, wherein the value of the gate resistor is increased prior to providing the gate switching signal to the transistor and decreased after measuring the rate of change of current through the converter during the switching period of the transistor (i.e., using a large gate resistance Rlarge during turn-on delay period and change the gate resistance to a small value Rlow afterward, see col. 6, lines 12-35; Fig. 3).
As for claim 8 and 9, Akin et al. discloses the method of claim 1, wherein the gate switching signal is provided to switch the transistor from a non-conducting state to a conducting state, or from a conducting state to a non-conducting state (i.e., both turn on or turn off delay time can be used for the junction temperature measurement; see col. 1, lines 36-43).
As for claim 10, Akin et al. discloses the method of claim 1, wherein the predetermined fraction is between around 0.75 and 0.95 (see Vds is around .75 to .95 range in Fig. 1).
As for claim 11, it is the apparatus/system claim corresponding to the method claim 1. It is rejected for the same reason as stated above for the rejection of claim 1.
As for claim 18, Akin et al. discloses the electrical power system of claim 11, wherein the transistor is a MOSFET (i.e., MOSFET transistor in Figs. 3, 4, 8 and Fig. 25).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3-5, 12-17 are rejected under 35 U.S.C. 103 as being unpatentable over Akin et al. (U. S. Patent 11,525,740), in view of Kimura et al. (U. S. Patent 11,016,138).
As for claims 3-5, 12-17, Akin et al. discloses the method/system of claims 1 and 11, wherein the converter comprises a plurality of transistors (see the two MOSFET transistors as shown in Fig. 25); and a controller (microcontroller in Fig. 4) provides the gate switching signal to the transistor; and the method is repeated for each one of the plurality of transistors (see the plurality of transistors in Fig. 25); and to receive the a measure of the threshold voltage (see the Vg reference in Fig. 3; col. 5, lines 39-40) for the transistor and output the corresponding junction temperature according to the measured threshold voltage.
Still referring to claims 3-5, 12-17, Akin et al. does not explicitly disclose the converter comprises: a capacitor connected across one of the supplies; and the rate of change of current is measured by a Rogowski coil located around a conductor of the converter between the plurality of transistors and the capacitor; and the measured rate of change of current is provided to an analogue to digital converter, ADC, the ADC provides a digital output signal from the measured rate of change of current to a processor, the processor synchronise and extracts a measurement of rate of change of current for the switching period; and a look-up table receives the extracted measurement of rate of change of current and outputs a corresponding junction temperature value for the transistor; and wherein the power electronics converter is configured to convert between a DC supply voltage and an AC supply voltage; or a current integrator configured to integrate the current signal from the current sensor and provide a measure of current through the converter as an input to the look-up table.
Kimura et al. discloses a conventional diagnosis system for measuring the junction temperature of the plurality of transistors in a power conversion system (see Figs. 1 and 4), wherein the converter comprises: a capacitor (5) connected across one the supplies (5); and the rate of change of current is measured by a Rogowski coil (4a—4f) located around a conductor of the converter between the plurality of transistors and the capacitor (5); and the measured rate of change of current is provided to an analogue to digital converter, ADC (ADC 23x and 23y in Fig. 4), the ADC (23x, 23Y) provides a digital output signal from the measured rate of change of current to a processor (parameter computing section 30), the processor (30) synchronise and extracts a measurement of rate of change of current for the switching period; and wherein the power electronics converter is configured to convert between a DC supply voltage (6) and an AC supply voltage (2); or wherein the junction temperature measurement module (20) further comprises a current integrator(22a) configured to integrate the current signal from the current sensor (4a—4f) and provide a measure of current through the converter as an input to processor (30).
It would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to modify Akin et al. to disclose using the specific circuit elements of the power converter including: the capacitor, the Rogowski coils, the ADC, DC and AC supply, the current integrator and the processor as taught by Kimura et al., and also with the addition of using a look up table for obtaining and outputting the corresponding junction temperatures for the transistors according to threshold voltage and the current measured, since using such circuit elements in the power converter system are just alternative design choices for a possible embodiment of the power converter system.
Claims 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Akin et al. (U. S. Patent 11,525,740) in view of EP3730408.
As for claims 19 and 20, Akin et al. discloses the system of claim 11 as discussed above.
Akin et al. does not specifically discloses an aircraft or aircraft propulsion system comprising the electric power system.
EP3730408 discloses an aircraft with an electric power system (see aircraft in Figs. 4 and 5 and the electric power system in Fig. 2).
It would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to modify Akin et al. to disclose using the electrical power converter system in an aircraft or an aircraft propulsion system, as taught by EP370408, for the purpose of accurately measuring the junction temperature of the plurality of transistors in the power converter system in the aircraft in real-time and with improved measurement accuracy and sensitivity by using the adjustable gate resistance circuit (see col. 6, lines 12-15 in Akin).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AMY HE whose telephone number is (571)272-2230. The examiner can normally be reached 9:00am--5:00pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Huy Phan can be reached at (571) 272-7924. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/AMY HE/Primary Examiner, Art Unit 2858