DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1, 10, and 19 recite “the upper outer sidewall being opposite to the inner sidewall…” It is unclear based on the claim language how the upper outer sidewall is supposed to be “opposite to” the inner sidewall. Are the two sidewalls opposite conductivity? Opposite doping? Opposite shape? Opposite position? If it is an opposite position, opposite relative to what? On opposite sides relative to a direction perpendicular to the top surface of the substrate? On opposite sides of the gate insulation layer in a direction relative to a direction parallel to the top surface of the substrate? Applicant has not provided enough detail in the claim language to allow one of ordinary skill to identify a specific interpretation of the claims.
Therefore, claims 1, 10, and 19 are rejected under 35 USC 112(b) for indefiniteness, and claims 2-9, 11-18 and 20 are rejected for at least their dependencies. Appropriate correction is required.
For the purposes of examination, any device will be interpreted to have an upper sidewall and a lower sidewall be “opposite to” each other in terms of the above claim language.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-12 and 14-19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by LEE et al. (US 20220102352 A1, hereinafter Lee)
With regards to claim 1, Lee discloses a semiconductor device, (FIGS. 4A-4C and 5B) comprising:
a substrate; (substrate 100)
a channel pattern (channel pattern CP) on the substrate, the channel pattern having sidewalls extending in a vertical direction perpendicular to a surface of the substrate and a lower portion connecting lower portions of two sidewalls facing each other in a horizontal direction; (See FIG. 4B/5B)
a gate insulation layer pattern (gate insulation Gox) and a first conductive layer pattern (word line WL1 and WL2) sequentially stacked laterally on an inner sidewall of the channel pattern; (See FIG. 4B/5B) and
a second conductive layer pattern (landing pad LP) contacting at least an uppermost surface and an upper outer sidewall of the channel pattern, the upper outer sidewall being opposite to the inner sidewall, (See above) the second conductive layer pattern being spaced apart from the first conductive layer pattern. (See FIG. 5B, where the landing pad LP contacts an upper portion and an upper outer sidewall of the channel CP)
With regards to claim 2, Lee discloses the semiconductor device as claimed in claim 1, wherein the channel pattern includes an oxide semiconductor. (Paragraph [0080]: ‘The channel patterns CP may be formed of or include at least one of oxide semiconductor materials (e.g., In.sub.xGa.sub.yZn.sub.zO…”)
With regards to claim 3, Lee discloses the semiconductor device as claimed in claim 1, wherein an uppermost surface of the first conductive layer pattern is higher than a bottom of the second conductive layer pattern. (see FIG. 4B/5B)
With regards to claim 4, Lee discloses the semiconductor device as claimed in claim 1, further comprising a capacitor (data storage pad DSP) on an upper surface of the second conductive layer pattern. (see FIG. 4B-4C)
With regards to claim 6, Lee discloses the semiconductor device as claimed in claim 1, further comprising a mold insulation structure (insulation layers 115/141 and 150) on an outer sidewall of the channel pattern, wherein the mold insulation structure includes:
a lower mold insulation pattern (layer 115/141) contacting the outer sidewall of the channel pattern; and
an upper mold insulation pattern (layer 150) on the lower mold insulation pattern, the upper mold insulation pattern being spaced apart from the upper outer sidewall of the channel pattern. (see FIG. 4B/5B)
With regards to claim 7, Lee discloses the semiconductor device as claimed in claim 6, wherein:
the lower mold insulation pattern includes silicon oxide, (Paragraph [0174]: ‘The first insulating pattern 115 may be formed of or include at least one of, for example, silicon oxide…”) and the upper mold insulation pattern includes silicon nitride. (Paragraph [0172]: “For example, the lower insulating layer 110 may include at least one of …a silicon nitride layer...”)
With regards to claim 8, Lee discloses the semiconductor device as claimed in claim 6, wherein a bottom of the second conductive layer pattern contacts an upper surface of the lower mold insulation pattern. (see FIG. 5B, showing the contact to the layer 141)
With regards to claim 9, Lee discloses the semiconductor device as claimed in claim 6, wherein a top surface of the second conductive layer pattern is higher than a top surface of the mold insulation structure. (see FIG. 5B, showing the landing pad LP higher than a top surface of layer 115/141)
With regards to claim 10, Lee discloses a semiconductor device, (FIGS. 4A-4C and 5B) comprising:
a substrate; (substrate 100)
a first conductive layer pattern (bit line) on the substrate, the first conductive pattern extending in a first direction parallel to an upper surface of the substrate; (See FIG. 4B)
a channel pattern (channel CP) on the first conductive layer pattern, the channel pattern having sidewalls extending in a vertical direction perpendicular to the upper surface of the substrate and a lower portion connecting lower portions of two sidewalls facing each other in the first direction, and the lower portion of the channel pattern contacting an upper surface of the first conductive layer pattern; (see FIG. 4B/5B)
a gate insulation layer pattern (insulation Gox) stacked on an inner sidewall of the channel pattern; (See FIG. 4B/5B)
a second conductive layer pattern (word lines WL1/WL2) on the gate insulation layer pattern;
a mold insulation structure (insulation layers 115and 150) on an outer sidewall of the channel pattern, the mold insulation structure including a lower mold insulation pattern (insulation layers 115) and an upper mold insulation pattern (insulation layers 150) stacked, the upper mold insulation pattern being spaced apart from an upper outer sidewall of the channel pattern; (see FIG. 4B/5B)
a third conductive layer pattern (landing pad LP) contacting at least an uppermost surface and the upper outer sidewall of the channel pattern, the upper outer sidewall being opposite to the inner sidewall, (See 112 rejection above) the third conductive layer pattern filling a space between the outer sidewall of the channel pattern and the upper mold insulation pattern; (see FIG. 5B) and
a capacitor (data storage pattern DSP) contacting an upper surface of the third conductive layer pattern. (See FIGS. 4B-4C)
With regards to claim 11, Lee discloses the semiconductor device as claimed in claim 10, wherein the channel pattern includes an oxide semiconductor. (Paragraph [0080]: ‘The channel patterns CP may be formed of or include at least one of oxide semiconductor materials (e.g., In.sub.xGa.sub.yZn.sub.zO…”)
With regards to claim 12, Lee discloses the semiconductor device as claimed in claim 10, wherein an uppermost surface of the second conductive layer pattern is lower than uppermost surfaces of the channel pattern and the gate insulation pattern. (see FIG. 4B/5B)
With regards to claim 14, Lee discloses the semiconductor device as claimed in claim 10, wherein:
a plurality of channel patterns are spaced apart from each other in each of the first directions and a second direction perpendicular to the first direction, the mold insulation structure is between the first direction of the channel pattern, and extends in the second direction. (see FIG. 4B/5B)
With regards to claim 15, Lee discloses the semiconductor device as claimed in claim 10, wherein a bottom of the third conductive layer pattern contacts an upper surface of the lower mold insulation pattern. (see FIG. 4B/5B)
With regards to claim 16, Lee discloses the semiconductor device as claimed in claim 10, wherein an uppermost surface of the third conductive layer pattern is higher than an upper surface of the mold insulation structure. (see FIG. 4B/5B)
With regards to claim 17, Lee discloses the semiconductor device as claimed in claim 10, further comprising a filling insulation pattern (dielectric 141) on the gate insulation layer pattern and the second conductive layer pattern, wherein the filling insulation pattern extends in a second direction perpendicular to the first direction while opposing the mold insulation structure in a horizontal direction. (see FIG. 4B/5B)
With regards to claim 18, Lee discloses the semiconductor device as claimed in claim 17, wherein the third conductive layer pattern fills a gap between the filling insulation pattern and the upper mold insulation pattern. (See FIG. 4B/5B)
With regards to claim 19, Lee discloses a semiconductor device, (FIGS. 4A-4C and 5B) comprising:
a substrate; (substrate 100)
a channel pattern (channel CP) on the substrate, the channel pattern having sidewalls extending in a vertical direction perpendicular to a surface of the substrate and a lower portion connecting lower portions of two sidewalls facing each other in a first direction parallel to an upper surface of the substrate; (see FIG. 4B/5B)
a gate insulation layer pattern (insulation Gox) and a first conductive layer pattern sequentially stacked laterally on an inner sidewall of the channel pattern; (see FIG. 4B/5B)
a mold insulation structure (insulation layers 115and 150) on an outer sidewall of the channel pattern, the mold insulation structure extending in a second direction perpendicular to the first direction, wherein an upper sidewall of the mold insulation structure is spaced apart from an upper outer sidewall of the channel pattern; (see FIG. 4B/5B)
a filling insulation pattern (dielectric 141) on the gate insulation layer pattern and the first conductive layer pattern, the filling insulation pattern extending in a second direction perpendicular to the first direction while opposing the mold insulation structure in a horizontal direction; (see FIG. 4B/5B) and
a second conductive layer pattern (landing pad LP) contacting at least an uppermost surface and an upper outer sidewall of the channel pattern, the upper outer sidewall being opposite to the inner sidewall, (See 112b rejection above) the second conductive layer pattern filling a space between the filling insulation pattern and the upper sidewall of the mold insulation structure. (See FIGS. 4B/5B)
Response to Arguments
Applicant's arguments filed 07/06/2026 have been fully considered but they are not persuasive.
Examiner notes that the amendments introduce a new issue under 35 USC 112b as recited above, as the term “opposite” is not relatively defined. Thus, claims 1-20 are properly rejected.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US 20220367721 A1 – vertical stacked channels and word lines
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEVEN M Page whose telephone number is (571)272-3249. The examiner can normally be reached M-F: 10:00AM-6:00PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine S. Kim can be reached at 571-272-8548. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/STEVEN M PAGE/Primary Patent Examiner, Art Unit 2812
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