DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restriction
Applicant’s election of Claims 17-20 without traverse has been acknowledged. Claims 1-16 were cancelled. Claims 17-37 are pending.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 32-33 and 35 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Madurawe et al (US 2020/0135795).
Regarding Claim 32, Madurawe et al discloses a method (forming [0003]), comprising:
forming a first photosensitive region (shown in annotated Fig 6 viewed from 180 degrees) in a first substrate (shown in annotated Fig 6 viewed from 180 degrees);
forming a transfer transistor (transfer transistor 44 [0025] Fig 6 viewed from 180 degrees) bordering the first photosensitive region (shown in annotated Fig 6 viewed from 180 degrees) and comprising a floating diffusion region (floating diffusion region 46A Fig 6 viewed from 180 degrees);
forming a first conductive stack (shown in annotated Fig 6 viewed from 180 degrees) overlying the first substrate (shown in annotated Fig 6 viewed from 180 degrees) and comprising a first metal line (vias 66A [0037] shown in annotated Fig 6 viewed from 180 degrees) and a second metal line (vias 66A [0037] shown in annotated Fig 6 viewed from 180 degrees) at a top of the first conductive stack (shown in annotated Fig 6 viewed from 180 degrees);
forming a first dielectric structure (first portion of isolation layer 42/interlayer dielectric layer [0032]- [0035] shown in annotated Fig 6 viewed from 180 degrees) over the first conductive stack (shown in annotated Fig 6 viewed from 180 degrees);
forming a first bond pad (metal pad 38A [0037] shown in annotated Fig 6 viewed from 180 degrees) and a second bond pad (metal pad 38A [0037] shown in annotated Fig 6 viewed from 180 degrees) inset into the first dielectric structure (first portion of isolation layer 42/interlayer dielectric layer [0032]- [0035] shown in annotated Fig 6) and extending respectively to the first (66A shown in annotated Fig 6 viewed from 180 degrees) and second metal lines (66A shown in annotated Fig 6 viewed from 180 degrees), wherein the first bond pad (38A shown in annotated Fig 6 viewed from 180 degrees) overlies the floating diffusion region (46A Fig 6 viewed from 180 degrees);
forming a plurality of transistors (transfer transistor 44, reset transistor 52, source follower transistor 54, row select transistor 56 [0025] Fig 6 viewed from 180 degrees) on a second substrate (shown in annotated Fig 6 viewed from 180 degrees);
forming a second conductive stack (shown in annotated Fig 6 viewed from 180 degrees) overlying and electrically coupled to the plurality of transistors (44,52,54,56 Fig 6 viewed from 180 degrees);
forming a third bond pad (metal pad 38B [0037] shown in annotated Fig 6 viewed from 180 degrees) and a fourth bond pad (metal pad 38B [0037] shown in annotated Fig 6 viewed from 180 degrees) overlying and electrically coupled to the second conductive stack (shown in annotated Fig 6 viewed from 180 degrees); and
bonding the third (38B shown in annotated Fig 6 viewed from 180 degrees) and fourth bond pads (38B shown in annotated Fig 6 viewed from 180 degrees) respectively to the first (38A shown in annotated Fig 6 viewed from 180 degrees) and second bond pads (38A shown in annotated Fig 6 viewed from 180 degrees) at a bond interface (interface between 38A and 38B) between the first (shown in annotated Fig 6 viewed from 180 degrees) and second substrates (shown in annotated Fig 6 viewed from 180 degrees),
wherein the bonding (bonding [0037]) forms a pixel circuit (pixel circuitry [0037]) comprising a capacitor with a first terminal defined by the first (38A shown in annotated Fig 6 viewed from 180 degrees) and third bond pads (38B shown in annotated Fig 6 viewed from 180 degrees) and a second terminal defined by the second (38A shown in annotated Fig 6 viewed from 180 degrees) and fourth bond pads (38B shown in annotated Fig 6 viewed from 180 degrees).
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Regarding Claim 33, Madurawe et al discloses the limitations of claim 32 as explained above. Madurawe et al further discloses
further comprising: forming a second dielectric structure (second portion of isolation layer 42/interlayer dielectric layer [0032]- [0035] shown in annotated Fig 6 viewed from 180 degrees) over the second conductive stack (shown in annotated Fig 6 viewed from 180 degrees), wherein the third (38B shown in annotated Fig 6 viewed from 180 degrees) and fourth bond pads (38B shown in annotated Fig 6 viewed from 180 degrees) are formed inset into the second dielectric structure (second portion of isolation layer 42/interlayer dielectric layer shown in annotated Fig 6 viewed from 180 degrees); and bonding the second dielectric structure (second portion of isolation layer 42/interlayer dielectric layer shown in annotated Fig 6 viewed from 180 degrees) to the first dielectric structure (first portion of isolation layer 42/interlayer dielectric layer shown in annotated Fig 6 viewed from 180 degrees) at the bond interface (interface between 38A and 38B) while bonding the third (38B shown in annotated Fig 6 viewed from 180 degrees) and fourth bond pads (38B shown in annotated Fig 6 viewed from 180 degrees) respectively to the first (38A shown in annotated Fig 6 viewed from 180 degrees) and second bond pads (38A shown in annotated Fig 6 viewed from 180 degrees).
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Regarding Claim 35, Madurawe et al discloses the limitations of claim 32 as explained above. Madurawe et al further discloses
wherein the plurality of transistors transfer transistor 44, reset transistor 52, source follower transistor 54, row select transistor 56 [0025] shown above in Fig 6 viewed from 180 degrees) comprise a source follower transistor (54 shown above in Fig 6 viewed from 180 degrees) and a reset transistor (52 shown above in Fig 6 viewed from 180 degrees) that form the pixel circuit.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 17, and 24 are rejected under 35 U.S.C. 103 as being unpatentable over Madurawe et al (US 2020/0135795) in view of Chen et al (US 2023/0089511).
Regarding Claim 17, Madurawe et al discloses a method (forming [0003]), comprising: for each of a first integrated circuit (IC) die (lower integrated circuit layer 36 [0030] Fig 6) and a second IC die (upper integrated circuit layer 34 [0030] Fig 6):
forming a first dielectric layer (first portion of isolation layer 42/interlayer dielectric layer [0032]- [0035] shown in annotated Fig 6) over a first upper conductive structure (left vias 66A/B [0035] shown in annotated Fig 6) and a second upper conductive structure (right vias 66A/B [0035] shown in annotated Fig 6);
forming a second dielectric layer (second portion of isolation layer 42/interlayer dielectric layer [0032]- [0035] shown in annotated Fig 6) over the first dielectric layer (first portion of isolation layer 42/interlayer dielectric layer shown in annotated Fig 6);
forming a first trench (area where 66A/B (left) is present shown in annotated Fig 6) and a second trench (area where 66A/B (right) is present shown in annotated Fig 6) through the second dielectric layer (second portion of isolation layer 42/interlayer dielectric layer shown in annotated Fig 6) and the first dielectric layer (first portion of isolation layer 42/interlayer dielectric layer shown in annotated Fig 6), the first trench (area where 66A/B (left) is present shown in annotated Fig 6) having a first width (shown in annotated Fig 6) and the second trench (area where lower 66A/B (right) is present shown in annotated Fig 6) having a second width (shown in annotated Fig 6) in a cross-sectional view;
forming a third trench (area where conductive structure 38A/B (left) [0031] is present shown in annotated Fig 6) within the first trench (area where 66A/B (left) is present shown in annotated Fig 6) through the second dielectric layer (second portion of isolation layer 42 shown in annotated Fig 6) and a fourth trench (area where 38A/B (right) is present shown in annotated Fig 6) within the second trench (area where 66A/B (right) is present shown in annotated Fig 6) through the second dielectric layer (second portion of isolation layer 42 shown in annotated Fig 6), the third trench (area where 38A/B (left) is present shown in annotated Fig 6) having a third width (shown in annotated Fig 6) greater than the first width (shown in annotated Fig 6) and the fourth trench (area where 38A/B (right) is present shown in annotated Fig 6) having a fourth width (shown in annotated Fig 6) greater than the second width (shown in annotated Fig 6) in the cross- sectional view; and
forming a first conductive element (left 66A/B and left 38A/B shown in annotated Fig 6) in the first trench (area where 66A/B (left) is present shown in annotated Fig 6) and the third trench (area where 38A/B (left) is present shown in annotated Fig 6) and a second conductive element (right 66A/B and right 38A/B shown in annotated Fig 6) in the second trench (area where 66A/B (right) is present shown in annotated Fig 6) and the fourth trench (area where 38A/B (right) is present shown in annotated Fig 6), the first conductive element (left 66A/B and left 38A/B shown in annotated Fig 6) contacting the first upper conductive structure (left vias 66A/B [0035] shown in annotated Fig 6), and the second conductive element (right 66A/B and right 38A/B shown in annotated Fig 6) contacting the second upper conductive structure (right vias 66A/B [0035] shown in annotated Fig 6); and
bonding (bonding [0037]) an upper surface (38B Fig 6) of the first IC die (36 Fig 6) to an upper surface (38A Fig 6) of the second IC die (34 Fig 6) to form a capacitor comprising the first conductive elements (left 66A/B and left 38A/B shown in annotated Fig 6) and the second conductive elements (right 66A/B and right 38A/B shown in annotated Fig 6).
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Madurawe et al does not directly disclose
etching a first trench and a second trench through the second dielectric layer and the first dielectric layer,
etching a third trench within the first trench through the second dielectric layer and a fourth trench within the second trench through the second dielectric layer.
Chen et al, in the related art of semiconductor devices that include IC structures, discloses
etching (etching process [0015] Fig 4) a first trench (first trench 212 (left) [0015] shown in annotated Fig 6) and a second trench (first trench 212 (right) [0015] shown in annotated Fig 6) through the second dielectric layer (insulator substrate 202 [0012] Fig 6) and the first dielectric layer (STI structure 204 [0015] Fig 6),
etching (etching process 224 [0015] Fig 8) a third trench (second trench 226 (left) [0020] shown in annotated Fig 8) within the first trench (first trench 212 (left) [0015] shown in annotated Fig 6) through the second dielectric layer (insulator substrate 202 [0012] Fig 6) and a fourth trench (second trench 226 (right) [0020] shown in annotated Fig 8) within the second trench (first trench 212 (right) [0015] shown in annotated Fig 6) through the second dielectric layer (insulator substrate 202 [0012] Fig 6).
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It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Madurawe et al to include etching a first trench and a second trench through the second dielectric layer and the first dielectric layer, etching a third trench within the first trench through the second dielectric layer and a fourth trench within the second trench through the second dielectric layer as taught by Chen et al in order to extend the opening [0015] which would allow for more control over the etching process. Further, a person of ordinary skill in the art would have recognized that etching the trenches would be a simple substitution of one known element for another to obtain predictable results (see MPEP 2143.I(B)) (suitable alternate).
Regarding Claim 24, the combination of Madurawe et al and Chen et al discloses the limitations of claim 17 as explained above. The combination of Madurawe et al and Chen et al further discloses
further comprising, for each of the first (36 Fig 6 Madurawe et al) and second IC dies (34 Fig 6 Madurawe et al):
forming sacrificial fill material (fill layer 218 [0018] Fig 7 Chen et al) in the first (shown above in annotated Fig 6 Chen et al) and second trenches (shown above in annotated Fig 6 Chen et al) before the etching of the third (shown above in annotated Fig 8 Chen et al) and fourth trenches (shown above in annotated Fig 8 Chen et al),
wherein the etching (etching process 224 [0015] Fig 8 Chen et al) of the third (shown above in annotated Fig 8 Chen et al) and fourth trenches (shown above in annotated Fig 8 Chen et al) is performed with the sacrificial fill material (218 Fig 7 Chen et al) in the first (shown above in annotated Fig 6 Chen et al) and second trenches (shown above in annotated Fig 6 Chen et al).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Madurawe et al (US 2020/0135795) in view of Chen et al (US 2023/0089511), and in further view of Jatou et al (US 2025/0228021).
Regarding Claim 18, the combination of Madurawe et al and Chen et al discloses the limitations of claim 17 as explained above. The combination of Madurawe et al and Chen et al does not directly disclose
wherein the bonding of the upper surface of the first IC die to the upper surface of the second IC die comprises a heat- based bonding.
Jatou et al, in the related art of semiconductor devices that include IC die, discloses
wherein the bonding of the upper surface of the first IC die to the upper surface of the second IC die comprises a heat- based bonding (may involve low temperature treatments of the bonded assembly [0062]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Madurawe et al and Chen et al to include wherein the bonding of the upper surface of the first IC die to the upper surface of the second IC die comprises a heat- based bonding as taught by Jatou et al in order to allow interdiffusion to join the pads [0062]. Further, a person of ordinary skill in the art would have recognized that having a temperature based bonding process would be a simple substitution of one known element for another to obtain predictable results (see MPEP 2143.I(B)) (suitable alternate).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Madurawe et al (US 2020/0135795) in view of Chen et al (US 2023/0089511), and in further view of Wei et al (US 2019/0157334).
Regarding Claim 19, the combination of Madurawe et al and Chen et al discloses the limitation of claim 17 as explained above. The combination of Madurawe et al and Chen et al does not directly disclose
further comprising: for each of the first IC die and the second IC die, planarizing the upper surface after forming the first and second conductive elements.
Wei et al, in the related art of semiconductor devices that include IC die, discloses
planarizing the upper surface (planarizing each die [0015]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Madurawe et al and Chen et al to include further comprising: for each of the first IC die and the second IC die, planarizing the upper surface after forming the first and second conductive elements as taught by Wei et al in order to avoid bubble or voids at the interface of the two dies which can lead to device failure and because it is important for achieving high yield of semiconductor devices [0015]. Further, a person of ordinary skill in the art would have recognized that having a smooth planarized surface would help increase the performance and reliability of the device (see MPEP 2143.I(D)).
Claim 34 is rejected under 35 U.S.C. 103 as being unpatentable over Madurawe et al (US 2020/0135795) in view of Palaniappan et al (US 2020/0286945).
Regarding Claim 34, Madurawe et al discloses the limitations of claim 32 as explained above. Madurawe et al does not disclose
wherein the pixel circuit comprises a first conversion gain transistor electrically coupled from the floating diffusion region to the first terminal and further comprises a second conversion gain transistor electrically coupled to the first terminal.
Palaniappan et al, in the related art of semiconductor devices that include IC die, discloses
wherein the pixel circuit comprises a first conversion gain transistor (120 [0050]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Madurawe et al to include wherein the pixel circuit comprises a first conversion gain transistor electrically coupled from the floating diffusion region to the first terminal and further comprises a second conversion gain transistor electrically coupled to the first terminal as taught by Palaniappan et al in order to provide the floating diffusion region with additional capacitance [0035]. Further, a person of ordinary skill in the art would have recognized that having additional capacitance would be advantageous in optimizing the electrical functioning capability of the device (see MPEP 2143.I(D)).
Allowable Subject Matter
Claims 25-31 are allowable.
Regarding Claim 25, Madurawe et al (US 2020/0135795) discloses a method (forming [0003]), comprising:
forming a first integrated circuit (IC) die (upper integrated circuit layer 34 [0030] Fig 6 viewed from 180 degrees), comprising:
forming a first photodetector (photodiode 62/pixel 22D-C [0034]- [0035] Fig 6 viewed from 180 degrees) and a second photodetector (photodiode 62/pixel 22B-A [0034]-[0035] Fig 6 viewed from 180 degrees) in a first substrate (shown in annotated Fig 6 viewed from 180 degrees), respectively at a first pixel region (shown in annotated Fig 6 viewed from 180 degrees) and a second pixel region (shown in annotated Fig 6 viewed from 180 degrees) that border;
forming a first conductive stack (shown in annotated Fig 6 viewed from 180 degrees) overlying the first substrate (shown in annotated Fig 6 viewed from 180 degrees),
wherein the first conductive stack (shown in annotated Fig 6 viewed from 180 degrees) comprises a first conductive element (vias 66A [0035] shown in annotated Fig 6 viewed from 180 degrees), a second conductive element (vias 66A [0035] shown in annotated Fig 6 viewed from 180 degrees), and a third conductive element (metal pad 38A shown in annotated Fig 6 viewed from 180 degrees) at a top of the first conductive stack (shown in annotated Fig 6 viewed from 180 degrees);
forming a second IC die (lower integrated circuit layer 36 [0030] Fig 6 viewed from 180 degrees), comprising:
forming a second conductive stack (shown in annotated Fig 6 viewed from 180 degrees) overlying a second substrate (shown in annotated Fig 6 viewed from 180 degrees), wherein the second conductive stack (shown in annotated Fig 6 viewed from 180 degrees) comprises a fourth conductive element (vias 66B [0036] shown in annotated Fig 6 viewed from 180 degrees), a fifth conductive element (vias 66B [0036] shown in annotated Fig 6 viewed from 180 degrees), and a sixth conductive element (metal pad 38B [0037] shown in annotated Fig 6 viewed from 180 degrees) at a top of the second conductive stack (shown in annotated Fig 6 viewed from 180 degrees); and
bonding (bonding [0037]) the first (34 Fig 6 viewed from 180 degrees) and second (36 Fig 6 viewed from 180 degrees) IC dies together,
wherein the bonding (bonding [0037]) comprises arranging the first (66A shown in annotated Fig 6 viewed from 180 degrees), second (66A shown in annotated Fig 6 viewed from 180 degrees), and third conductive elements (38A shown in annotated Fig 6 viewed from 180 degrees) in contact respectively with the fourth (66B shown in annotated Fig 6 viewed from 180 degrees), fifth (66B shown in annotated Fig 6 viewed from 180 degrees), and sixth conductive elements (38B shown in annotated Fig 6 viewed from 180 degrees);
wherein the first (66A shown in annotated Fig 6 viewed from 180 degrees) and second conductive elements (66A shown in annotated Fig 6 viewed from 180 degrees) respectively overlie the first (shown in annotated Fig 6 viewed from 180 degrees) and second pixel regions (shown in annotated Fig 6 viewed from 180 degrees), and
wherein the bonding (bonding [0037]) forms a first capacitor individual to the first pixel region (shown in annotated Fig 6 viewed from 180 degrees) from the first (66A shown in annotated Fig 6 viewed from 180 degrees), third (38A shown in annotated Fig 6 viewed from 180 degrees), fourth (66B shown in annotated Fig 6 viewed from 180 degrees), and sixth conductive elements (38B shown in annotated Fig 6 viewed from 180 degrees) and further forms a second capacitor individual to the second pixel region (shown in annotated Fig 6 viewed from 180 degrees) from the second (66A shown in annotated Fig 6 viewed from 180 degrees), third (38A shown in annotated Fig 6 viewed from 180 degrees), fifth (66B shown in annotated Fig 6 viewed from 180 degrees), and sixth conductive elements (38B shown in annotated Fig 6 viewed from 180 degrees).
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The reason for the indication of allowability of Claim 25 is the inclusion of
the third conductive element overlies a boundary between the first and second pixel regions.
Specifically, Madurawe et al does not disclose a conductive element that overlies a boundary between the first and second pixel regions as interpreted, and should another reference be found that discloses this limitation, it would not be obvious to a person of ordinary skill in the art to combine the references and make this alteration to Madurawe et al.
It is these features found in the claim, as they are claimed in the combination that has not been found, taught or suggested by the prior art of record, which makes this claim allowable over the prior art.
Claims 21-23 and 36-37 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 21:
Regarding Claim 21, the combination of Madurawe et al and Chen et al discloses the limitations of claim 17 as explained above. Madurawe et al (US 2020/0135795) further discloses
further comprising, for the first IC die (36 Fig 6 Madurawe et al): forming a first pixel (pixels 22A 0035] Fig 6 Madurawe et al) and a second pixel (pixels 22B [0035] Fig 6 Madurawe et al) on a substrate (shown above in annotated Fig 6 Madurawe et al) of the first IC die (36 Fig 6 Madurawe et al),
wherein the first (22A Fig 6 Madurawe et al) and second pixels (22B Fig 6 Madurawe et al) border and respectively comprise a first photodetector (left photodiode 62 corresponding to 22A [0035] Fig 6 Madurawe et al) and a second photodetector (right photodiode 62 [0035] Fig 6 Madurawe et al), and
wherein the first conductive element (left 66A/B and left 38A/B shown above in annotated Fig 6 Madurawe et al) of the first IC die (36 Fig 6 Madurawe et al) is formed overlying a center of the first pixel (22A Fig 6 Madurawe et al).
The reason for the indication of allowability of Claim 21 is the inclusion of
the second conductive element of the first IC die is formed overlying a boundary between the first and second pixels.
Specifically, in this interpretation, the combination of Madurawe et al and Chen et al does not disclose this claim limitation because the second conductive element (right 66A/B and right 38A/B shown above in annotated Fig 6 Madurawe et al) of the first IC die (36 Fig 6 Madurawe et al) does not overly a boundary between the first (22A Fig 6 Madurawe et al) and second pixels (22B Fig 6 Madurawe et al). Further, should a different interpretation be used, i.e. the first pixel is 22A and 22B, and the second pixel is 22C and 22D, the second conductive element would still not overly a boundary between the first and second pixel, and a similar result occurs if the first pixel is 22C and 22D and the second pixel is 22A and 22B as the first conductive element would overly a center if the first pixel but the second conductive element would still not meet the requirement of overlying a boundary between the first and second pixel. Additionally, should another reference be found that meets this limitation it would not be obvious to a person of ordinary skill in the art to combine the references to make this alteration to the combination of Madurawe et al and Chen et al.
It is these features found in the claim, as they are claimed in the combination that has not been found, taught or suggested by the prior art of record, which makes this claim allowable over the prior art.
Claim 22 would be allowable based on its dependency on Claim 21.
Claim 23:
Regarding Claim 23, the combination of Madurawe et al and Chen et al discloses the limitations of claim 17 as explained above.
The reason for the indication of allowability of Claim 23 is the inclusion of
wherein the second conductive element of the first IC die is formed with a mesh-shaped top geometry and extends in a closed path around the first conductive element.
Specifically, the combination of Madurawe et al and Chen et al does not disclose this claim limitation and should another reference be found that discloses a mesh-shaped top geometry for a conductive element, it would not be obvious to a person of ordinary skill in the art to modify the combination of Madurawe et al and Chen et al to include it for the second conductive element because it is also required to extend in a closed path around the first conductive element.
It is these features found in the claim, as they are claimed in the combination that has not been found, taught or suggested by the prior art of record, which makes this claim allowable over the prior art.
Claim 36:
Regarding Claim 36, Madurawe et al discloses the limitations of claim 17 as explained above.
Chen et al (US 2023/0089511) discloses
performing a first etch (etching process [0015] Fig 4) into the first dielectric structure (STI structure 204 [0015] Fig 6) to form a first pair of trenches (first trench 212 (left) and first trench 212 (right) [0015] shown in annotated Fig 6) with a first depth (shown in Fig 6);
filling the first pair of trenches (first trench 212 (left) and first trench 212 (right) [0015] shown in annotated Fig 6) with sacrificial material (fill layer 218 [0018] Fig 7);
performing a second etch (etching process 224 [0015] Fig 8) into the first dielectric structure (STI structure 204 [0015] Fig 6) to form a second pair of trenches (second trench 226 (left) and second trench 226 (right) [0020] shown in annotated Fig 8) respectively overlapping with the first pair of trenches (first trench 212 (left) and first trench 212 (right) [0015] shown in annotated Fig 6) and having a second depth (shown in annotated Fig 8) less than the first depth (shown in annotated Fig 6); and
filling (shown in Fig 7) the first pairs of trenches with conductive material (218 may be conductive [0018]).
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The reason for the indication of allowability of Claim 36 is the inclusion of
filling the second pairs of trenches with conductive material.
Specifically, Madurawe et al and Chen et al does not disclose this feature since Chen et al on discloses filling the first pairs of trenches with conductive material and not the second pairs of trenches. Further, should a new reference be found that discloses conductive material in the second trenches, it would not be obvious to a person of ordinary skill in the art to combine the references to make this alteration to the combination of Madurawe et al and Chen et al.
It is these features found in the claim, as they are claimed in the combination that has not been found, taught or suggested by the prior art of record, which makes this claim allowable over the prior art.
Claim 37 would be allowable based on its dependency on Claim 36.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Related Cited Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Rhodes (US 2005/0148114) which discloses a conventional CMOS imager [0002], and McKee (US 2007/0023798) which discloses a CMOS imager with a dual conversion gain transistor and capacitor embodiments [0057].
Conclusion
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/D.P.S./Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
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