CTNF 18/425,332 CTNF 90618 Notice of AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. DETAILED ACTION Drawings 06-36 AIA The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “an interposer between a semiconductor chip and a wiring structure” must be shown or the feature(s) canceled from the claim(s). No new matter should be entered. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Note that the semiconductor chip as claimed in claim 10, Line 3: “the semiconductor chip is disposed in the additional cavity”. If this correct then the limitation of claim 11: “an interposer between a semiconductor chip and a wiring structure” cannot be correct dues figures and specification [0032]. It appears that claim 11 intends to claim the following: “an interposer between the wiring structure and the additional semiconductor chip”. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15 AIA Claim s 1-4, 7-10, 14 and 20 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Sung et al. , hereinafter, Sung104 (US 2021/0100104 A1) . Regarding independent claim 1: Sung104 teaches (e.g., Fig. 3) a semiconductor package comprising: a wiring structure ([0035]-[0038] and [0042]: 122) having an alternating structure of at least one first wiring layer ([0035]-[0038]: 122a) and at least one first insulating layer ([0035]-[0038]: 121a); a semiconductor chip ([0042]: 310) overlapping the wiring structure in a stacking direction of the wiring structure; a second insulating layer ([0034]: 111) overlapping the wiring structure in the stacking direction of the wiring structure and including a cavity ([0034] and [0040]: inner portion 111H); an inductor ([0040]: 200A) in the cavity and electrically connected to the semiconductor chip (310); a lead-out pillar ([0040]: 113a1) extending from one surface of the inductor facing the wiring structure, and electrically connecting the inductor (200A) and the semiconductor chip (310); and an encapsulant ([0034], [0057]: 210/241/242) encapsulating the inductor, wherein the inductor includes an insulating body ([0055] and [0062]: 220/210) and a coil portion ([0040]: 231/232) disposed in the insulating body (220/210), the coil portion configured to output a magnetic field in a direction ([0040]: the coil portion 231/232 is capable of output a magnetic field in a direction; the wiring is wrapping around a core portion that produces a magnetic field in the horizontal direction), different from the stacking direction of the wiring structure ([0035]-[0038]: the stacking direction of 122a and 122c are stacked in the vertical direction different from the horizontal direction), and wherein a first region on one surface of the insulating body (Fig. 3 and Fig. 5: [0055] and [0062]: 220/210) using the left side coils 232, the right side portion) facing the wiring structure and not overlapping the lead-out pillar ([0040]: 113a1) is in direct contact with the encapsulant or the at least one first insulating layer ([0055] and [0062]: 220/210). Regarding claim 2: Sung104 teaches the claim limitation of the semiconductor package of claim 1, on which this claim depends, wherein an area of the first region (Fig. 3 and Fig. 5: [0055] and [0062]: 220/210) using the left side coils 232, the right portion) is greater than an area of a second region (Fig. 3 and Fig. 5: [0055] and [0062]: 220/210) using the left side coils 232, the left side portion) on the one surface of the insulating body (220/210) and overlapping the lead-out pillar (113a1). Regarding claim 3: Sung104 teaches the claim limitation of the semiconductor package of claim 1, on which this claim depends, wherein the lead-out pillar ([0040]: 113a1) extends from a position laterally offset from a center of the one surface of the insulating body ([0055] and [0062]: 220/210). Regarding claim 4: Sung104 teaches the claim limitation of the semiconductor package of claim 1, on which this claim depends, wherein a portion of the lead-out pillar ([0040]: 113a1) passes through a portion of the encapsulant ([0034], [0057]: 210/241/242), and a different portion of the lead-out pillar passes through the at least one first insulating layer (121a). Regarding claim 7: Sung104 teaches the claim limitation of the semiconductor package of claim 1, on which this claim depends, wherein the at least one first wiring layer includes a plurality of first wiring layers ([0035]: 122a and 122b), and the at least one first insulating layer includes a plurality of first insulating layers ([0034] and [0036]: 121a and 121b), wherein the second insulating layer (111) is between upper and lower portions of the plurality of first wiring layers (122a and 122b) and is between upper and lower portions of the plurality of first insulating layers (121a and 121b). Regarding claim 8: Sung104 teaches the claim limitation of the semiconductor package of claim 7, on which this claim depends, wherein a thickness of the second insulating layer (111) is greater than a thickness of each of the plurality of first insulating layers (121a and 121b). Regarding claim 9: Sung104 teaches the claim limitation of the semiconductor package of claim 7, on which this claim depends, further comprising: an additional lead-out pillar ([0040]: 113b1) extending from the other surface of the insulating body of the inductor opposing the one surface of the insulating body of the inductor from which the lead-out pillar extends (113a1), wherein the lead-out pillar (113a1) and the additional lead-out pillar (113b1) extend in opposite directions at positions laterally offset from centers of the one surface and the other surface of the insulating body ([0055] and [0062]: 220/210), respectively. Regarding claim 10: Sung104 teaches the claim limitation of the semiconductor package of claim 1, on which this claim depends, wherein the second insulating layer (111) provides an additional cavity, and the semiconductor chip ([0042]: 310) is disposed in the additional cavity. Regarding claim 1 4: Sung104 teaches the claim limitation of the semiconductor package of claim 1, on which this claim depends, wherein the insulating body comprises magnetic powder particles ([0060]) and an insulating resin ([0061]-[0062]). Regarding independent claim 20: Sung104 teaches (e.g., Fig. 3) a semiconductor package comprising: a wiring structure ([0035]-[0038] and [0042]: 122a) having an alternating structure of at least one first wiring layer ([0035]-[0038]: 122a) and at least one first insulating layer ([0035]-[0038]: 121A); a semiconductor chip ([0042]: 310) overlapping the wiring structure in a stacking direction of the wiring structure; a second insulating layer ([0034]: 111) overlapping the wiring structure in the stacking direction of the wiring structure and including a cavity ([0034] and [0040]: inner portion 111H); an inductor ([0040]: 200A) in the cavity and electrically connected to the semiconductor chip (310); a lead-out pillar ([0040]: 113a1) extending from one surface of the inductor facing the wiring structure and electrically connecting the inductor (200A) and the semiconductor chip; an additional lead-out pillar ([0040]: 113b1) extending from the other surface of an insulating body of the inductor opposing the one surface of the insulating body of the inductor; and an encapsulant ([0034], [0057]: 210/241/242) encapsulating the inductor, wherein the inductor includes the insulating body ([0055] and [0062]: 220/210), and a coil portion ([0040]: 231/232) in the insulating body, the coil portion configured to output a magnetic field ([0040]: the coil portion 231/232 is capable of output a magnetic field in a direction; the wiring is wrapping around a core portion that produces a magnetic field in the horizontal direction) in a direction, different from the stacking direction of the wiring structure (vertical direction), the at least one first wiring layer includes a plurality of first wiring layers ([0035]-[0038]: 122a and 122b), the at least one first insulating layer includes a plurality of first insulating layers ([0035]-[0038]: 121a and 121b); a first portion of the lead-out pillar ([0040]: 113a1) and a first portion of the additional lead-out pillar ([0040]: 113b1) pass through a portion of the encapsulant ([0034], [0057]: 210/241/242), a second portion of the lead-out pillar (upper portion of 113a1) and a second portion of the additional lead-out pillar (lower portion of 113b1) pass through upper and lower portions of the plurality of first insulating layers (121a and 121b), respectively, the first portion (closer portion) of the lead-out pillar (113a) and the first portion of the additional lead-out pillar (113b1) being different from the second portion (further portion) of the lead-out pillar (113a1) and the second portion of the additional lead-out pillar (113b1), respectively, and the lead-out pillar (113a1) and the additional lead-out pillar (13b1) extend in opposite directions (upward and downward, respectively) at positions laterally offset from centers of the one surface and the other surface of the insulating body (220/210), respectively . Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Sung et al. , hereinafter, Sung104 (US 2021/0100104 A1) in view of Zhao et al. (US 2015/0302974 A1) . Regarding claim 5: Sung104 teaches the claim limitation of the semiconductor package of claim 4, on which this claim depends, wherein the wiring structure comprises wiring vias ([0036] and [0050]: 123a/123c) connected to the at least one first wiring layer and passing through the at least one first insulating layer ([0035]-[0038]: 121a). Sung104 does not expressly teach that a width of the portion of the lead-out pillar passing through the portion of the encapsulant is greater than a width of each of the wiring vias. Zhao teaches (e.g., Fig. 8A) a semiconductor package comprising a lead-out pillar ([0034]-[0035]: lead pillar directly contacting inductor 830) and wiring vias ([0034]-[0035]: 832 of wiring located in layers 824); Zhao further teaches that a width of the portion of the lead-out pillar ([0034]-[0035]: lead pillar directly contacting inductor 830) passing through the portion of an encapsulant ([0034]-[0035]: 820) is greater than a width of each of the wiring vias ([0034]-[0035]: 832 of wiring located in layers 824). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, the semiconductor package comprising a lead-out pillar, wherein the width of the portion of the lead-out pillar passing through the portion of the encapsulant is greater than a width of each of the wiring vias, as taught by Zhao, for the benefits of increasing the contact areas of the lead-out pillar to the inductor, thus reducing contact resistance and improving the signal speed to the inductor . 07-21-aia AIA Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Sung et al., hereinafter, Sung104 (US 2021/0100104 A1) in view of Bhagavat et al. (US 2020/0312766 A1) . Regarding claim 6: Sung104 teaches the claim limitation of the semiconductor package of claim 1, on which this claim depends, Sung104 does not expressly teach that the semiconductor chip comprises a voltage regulator. Bhagavat teaches (e.g., Fig. 2) a semiconductor chip comprising a voltage regulator ([0054]: 192). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, the semiconductor package comprising a voltage regulator, as taught by Bhagavat, for the benefit of regulating the voltage of the integrated circuit and reduce volage spikes that could damage the device circuits, and thus improve device reliability . 07-21-aia AIA Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Sung et al., hereinafter, Sung104 (US 2021/0100104 A1) in view of Kang et al. (US 2019/0333837 A1) . Regarding claim 11: Sung104 teaches the claim limitation of the semiconductor package of claim 1, on which this claim depends, further comprising: an additional semiconductor chip ([0041]: 320) electrically connected to the at least one first wiring layer (122a). Sung104 does not expressly teach an interposer between the semiconductor chip and the wiring structure and between the additional semiconductor chip and the wiring structure. Kang teaches (e.g., Fig. 9) a semiconductor package comprising an interposer ([0089]: 210) between an additional semiconductor chip ([0098]: 224) and a wiring structure ([0079]: 142a). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to include in the semiconductor package of Sung104, the interposer between the additional semiconductor chip and the wiring structure, as taught by Kang for the benefits of increasing the stacking density of the integrated circuit, thus increasing the functions of the device due to integration of a plurality of diverse chips on the same substrate . 07-21-aia AIA Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Sung et al., hereinafter, Sung104 (US 2021/0100104 A1) in view of Dosluoglu (US 2016/0233192 A1) . Regarding claim 12: Sung104 teaches the claim limitation of the semiconductor package of claim 1, on which this claim depends, further comprising: Sung104 does not expressly teach an additional inductor in the cavity, wherein the inductor and the additional inductor is configured to output magnetic fields in a same direction. Dosluoglu teaches (e.g., Figs. 1-5) a semiconductor package comprising an inductor ([0029]: 119a) in a cavity (cavity inside 113); Dosluoglu further teaches an additional inductor ([0029]: 119b) in a cavity ([0020] and [0022]: cavity inside 113 for inductors), wherein the inductor ([0029]: 119a) and the additional inductor ([0029]: 119b) is configured to output magnetic fields in a same direction ([0029]: inductor and additional inductor have the same structure and orientation; thus, they are configured to output magnetic fields in a same direction). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to include in the device of Sung104, the additional inductor in the cavity, wherein the inductor and the additional inductor are configured to output magnetic fields in a same direction, as taught by Dosluoglu, for the benefits of increasing the magnetic strength of the inductive structure and thus increasing the voltage regulator efficiency . 07-21-aia AIA Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Sung et al., hereinafter, Sung104 (US 2021/0100104 A1) in view of Kim et al. (US 2020/0286819 A1) . Regarding claim 13: Sung104 teaches the claim limitation of the semiconductor package of claim 1, on which this claim depends, further comprising: Sung104 does not expressly teach a conductive support layer directly contacting the other surface of the insulating body opposing the one surface of the insulating body from which the lead-out pillar extends, the conductive support layer directly contacting the second insulating layer. However, Sung104 teaches that the insulating body and the second insulating layer are coplanar (Fig. 3). Kim teaches (e.g., Fig. 2) a semiconductor package comprising a conductive support layer ([0041]: portion of structure 241 not connected to interconnect, that is the floating portion); Kim further teaches that the conductive support layer ([0041]: portion of structure 241 not connected to interconnect, that is the floating portion) is directly contacting a second insulating layer ([0050]: 21). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to include in the device of Sung104, the conductive support layer directly contacting the second insulating layer, as taught by Kim, for the benefits of reinforcing the rigidity of the core substrate and thus avoid mechanical damage to the device, this in turn, improving the device reliability. Since, Sung104 teaches that the insulating body and the second insulating layer are coplanar, Sung104 as modified by Kim, teaches that the conductive support layer directly contacting the other surface of the insulating body opposing the one surface of the insulating body from which the lead-out pillar extends, the conductive support layer directly contacting the second insulating layer, because the conductive support layer of Kim being in direct contact with the second insulating layer, would necessarily be in direct contact with the insulating body, which is coplanar with the second insulating layer, of Sung104. The requirement of the claimed limitation, is thus met, for the benefits, mentioned above . 07-21-aia AIA Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Sung et al. , hereinafter, Sung104 (US 2021/0100104 A1) in view of Sung et al., hereinafter Sung021 (US 10,842,021 B1) . Regarding claim 15: Sung104 teaches the claim limitation of the semiconductor package of claim 1, on which this claim depends, wherein the coil portion comprises a first coil pattern (Fig. 3 and Fig. 5; left side coil pattern 231) and a second coil pattern (Fig. 3 and Fig. 5; right side coil pattern 232), and the inductor further comprises, a support member ([0055]: Figs. 4-7; #220) between the first and second coil patterns, and a coil via ([0062]: 220H) passing through the support member, and in each of the first and second coil patterns, a thickness T1 is greater than a width W1 (Fig. 4; the thickness is in the third direction and the width in the second direction). Sung104 does not expressly teach that a coil via passing through the support member and electrically connecting the first and second coil patterns. Sung021 teaches (e.g., Figs. 5-6) a semiconductor package comprising a coil via (Col. 11. Lines 16-26: #112V) electrically connecting the first and second coil patterns (Col. 11. Lines 16-26: 112A and 112B respectively). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to include in the first coil pattern and second coil pattern, the coil via electrically connecting the first and second coil patterns, as taught by Sung021, for the benefits of increasing the inductance of the device and energy efficiency, including reducing energy losses and improving energy delivery . 07-21-aia AIA Claim s 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Sung et al., hereinafter, Sung104 (US 2021/0100104 A1) in view of Bharath et al. (US 2021/0098436 A1) . Regarding claim 16: Sung104 teaches the claim limitation of the semiconductor package of claim 1, on which this claim depends, wherein the insulating body (Figs. 3-4; [0040]) has a first surface and a second surface (top and bottom surfaces respectively) facing the wiring structure and opposing each other, a third surface and a fourth surface (left side and right side surfaces respectively) facing the second insulating layer and opposing each other, and a fifth surface and a sixth surface (front side and back side surfaces; corresponding to first direction as shown in Fig. 3) facing the second insulating layer and opposing each other. Sung does not expressly teach that a distance (Z1) between the first and second surfaces is greater than a distance (Y1) between the third and fourth surfaces, is greater than a distance (X1) between the fifth and sixth surfaces, and is greater than a thickness (Z2) of the second insulating layer. Bharath teaches (e.g., Figs. 1-3B) a semiconductor package comprising an inductor ([0030], [0033]-[0044]: PTH used for the inductor, see [0030]) a distance (Z1) between a first and second surfaces (top and bottom surfaces respectively) is greater than a distance (Y1) between the third and fourth surfaces (left side and right side surfaces respectively), is greater than a distance (X1) between the fifth and sixth surfaces (front side and back side surfaces; corresponding to first direction as shown in Fig. 3B), and is greater than a thickness (Z2) of the second insulating layer ([0031]-[0032]: 108; inductor is taller the second insulating layer). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to adjust the dimensions of the inductor of Sung, such that it includes the dimensions of the inductor of Bharath, for the benefits of conforming to the electromagnetic constraints of the device and avoid possible magnetic interferences of the device in operation. Regarding independent claim 17: Sung104 teaches (e.g., Fig. 3) a semiconductor package comprising: a wiring structure ([0035]-[0038]: 122a) having an alternating structure of at least one first wiring layer ([0035]-[0038]: 122a) and at least one first insulating layer ([0035]-[0038]: 121a); a semiconductor chip ([0042]: 310) overlapping the wiring structure in a stacking direction of the wiring structure; a second insulating layer ([0034]: 111) overlapping the wiring structure in the stacking direction of the wiring structure and including a cavity ([0034] and [0040]: inner portion 111H); an inductor ([0040]: 200A) in the cavity and electrically connected to the semiconductor chip (310); and a lead-out pillar ([0040]: 113a1) extending from one surface of the inductor facing the wiring structure and electrically connecting the inductor (200A) and the semiconductor chip (310), wherein the inductor includes an insulating body ([0055] and [0062]: 220/210) and a coil portion ([0040]: 231/232) in the insulating body, wherein the insulating body (Figs. 3-4; [0040]) has a first surface and a second surface (top and bottom surfaces respectively) facing the wiring structure and opposing each other, a third surface and a fourth surface (left side and right side surfaces respectively) facing the second insulating layer and opposing each other, and a fifth surface and a sixth surface (front side and back side surfaces; corresponding to first direction as shown in Fig. 3) facing the second insulating layer and opposing each other. Sung does not expressly teach that a distance (Z1) between the first and second surfaces is greater than a distance (Y1) between the third and fourth surfaces, is greater than a distance (X1) between the fifth and sixth surfaces, and is greater than a thickness (Z2) of the second insulating layer. Bharath teaches (e.g., Figs. 1-3B) a semiconductor package comprising an inductor ([0030], [0033]-[0044]: PTH used for the inductor, see [0030]) a distance (Z1) between a first and second surfaces (top and bottom surfaces respectively) is greater than a distance (Y1) between the third and fourth surfaces (left side and right side surfaces respectively), is greater than a distance (X1) between the fifth and sixth surfaces (front side and back side surfaces; corresponding to first direction as shown in Fig. 3B), and is greater than a thickness (Z2) of the second insulating layer ([0031]-[0032]: 108; inductor is taller the second insulating layer). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to adjust the dimensions of the inductor of Sung, such that it includes the dimensions of the inductor of Bharath, for the benefits of conforming to the electromagnetic constraints of the device and avoid possible magnetic interferences of the device in operation . 07-21-aia AIA Claim s 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Sung et al., hereinafter, Sung104 (US 2021/0100104 A1) in view of Bharath et al. (US 2021/0098436 A1) as applied above and further in view of in view of Sung et al., hereinafter Sung021 (US 10,842,021 B1) . Regarding claim 18: Sung104 and Bharath teach the claim limitation of the semiconductor package of claim 17, on which this claim depends, wherein the insulating body comprises magnetic powder particles ([0061]-[0062]) and an insulating resin ([0061]-[0062]), the coil portion comprises a first coil pattern (Fig. 3 and Fig. 5; left side coil pattern 231) and a second coil pattern (Fig. 3 and Fig. 5; right side coil pattern 232), a thickness T1 of each of the first and second coil patterns (Fig. 3 and Fig. 5; left side coil 231 and right side coil pattern 232) being greater that a width W1 thereof (Fig. 4; the thickness is in the third direction and the width in the second direction), and the inductor further comprises, a support member ([0055]: Figs. 4-7; #220) between the first and second coil patterns. Sung104 does not expressly teach a coil via passing through the support member and electrically connecting the first and second coil. Sung021 teaches (e.g., Figs. 5-6) a semiconductor package comprising a coil via (Col. 11. Lines 16-26: #112V) electrically connecting the first and second coil patterns (Col. 11. Lines 16-26: 112A and 112B respectively). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to include in the first coil pattern and second coil pattern, the coil via electrically connecting the first and second coil patterns, as taught by Sung021, for the benefits of increasing the inductance of the device and energy efficiency, including reducing energy losses and improving energy delivery. Regarding claim 19: Sung104, Bharath and Sung021 teach the claim limitation of the semiconductor package of claim 18, on which this claim depends, further comprising: an additional lead-out pillar ([0040]: 113b1) extending from the other surface of the insulating body ([0055] and [0062]: 220/210) of the inductor opposing the one surface of the insulating body of the inductor from which the lead-out pillar extends (113a1), wherein the lead-out pillar (112a1) and the additional lead-out pillar (113b1) extend in opposite directions at positions laterally offset from centers of the one surface and the other surface of the insulating body (220/210), respectively, the at least one first wiring layer includes a plurality of first wiring layers ([0035]: 122a and 122b), the at least one first insulating layer includes a plurality of first insulating layers ([0034] and [0036]: 121a and 121b), the second insulating layer is between upper and lower portions of the plurality of first wiring layers (122a and 122b), and is between upper and lower portions of the plurality of first insulating layers (121a and 121b), and a thickness of the second insulating layer (111) is greater than a thickness of each of the plurality of first insulating layers (121a and 121b). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to HERVE-LOUIS Y ASSOUMAN whose telephone number is (571)272-2606. The examiner can normally be reached M-F: 08:30 AM-5:30 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, DAVIENNE MONBLEAU can be reached at 571-272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /HERVE-LOUIS Y ASSOUMAN/Examiner, Art Unit 2812 Application/Control Number: 18/425,332 Page 2 Art Unit: 2812 Application/Control Number: 18/425,332 Page 3 Art Unit: 2812 Application/Control Number: 18/425,332 Page 4 Art Unit: 2812 Application/Control Number: 18/425,332 Page 5 Art Unit: 2812 Application/Control Number: 18/425,332 Page 6 Art Unit: 2812 Application/Control Number: 18/425,332 Page 7 Art Unit: 2812 Application/Control Number: 18/425,332 Page 8 Art Unit: 2812 Application/Control Number: 18/425,332 Page 9 Art Unit: 2812 Application/Control Number: 18/425,332 Page 10 Art Unit: 2812 Application/Control Number: 18/425,332 Page 11 Art Unit: 2812 Application/Control Number: 18/425,332 Page 12 Art Unit: 2812 Application/Control Number: 18/425,332 Page 13 Art Unit: 2812 Application/Control Number: 18/425,332 Page 14 Art Unit: 2812 Application/Control Number: 18/425,332 Page 15 Art Unit: 2812 Application/Control Number: 18/425,332 Page 16 Art Unit: 2812 Application/Control Number: 18/425,332 Page 17 Art Unit: 2812 Application/Control Number: 18/425,332 Page 18 Art Unit: 2812 Application/Control Number: 18/425,332 Page 19 Art Unit: 2812 Application/Control Number: 18/425,332 Page 20 Art Unit: 2812 Application/Control Number: 18/425,332 Page 21 Art Unit: 2812
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