Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6 and 12-16 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Pat. Pub. No. 20230039094 to Jang et al. (Jang) in view of U.S. Pat. No. 5191174 to Chang et al. (Chang).
Regarding Claim 1, Jang teaches in Fig. 1 at least, an integrated circuit (IC) package, comprising:
a die 200 comprising a plurality of die interconnects 230, the plurality of die interconnects comprising:
a first plurality of die interconnects 300a; and
a second plurality of die interconnects 300b; and
a substrate 100 comprising:
a first metallization layer 110a extending in a first direction (left to right of page), the first metallization layer comprising a first plurality of metal pads 120a wherein the first metallization layer is between the die and the second metallization layer (see Fig. 2A); and
a second metallization layer 110b extending in the first direction and parallel to the first metallization layer, the second metallization layer comprising a second plurality of metal pads 120b,
wherein the first plurality of die interconnects extend in a second direction orthogonal to the first direction and terminate at the first plurality of metal pads, and wherein the second plurality of die interconnects extend in the second direction and through the first metallization layer to terminate at the second plurality of metal pads (see Fig. 1).
Jang does not explicitly teach that the first plurality of die interconnects is interleaved between the second plurality of die interconnects so that each of the second plurality of die interconnects has at least one of the first plurality of die interconnects as a nearest neighbor in the first direction, and each of the second plurality of die interconnects has at least one of the first plurality of metal pads as a nearest neighbor in the first direction.
However, in analogous art, Chang teaches in Fig. 4 at least, first die interconnects 35 interleaved and adjacent to each of second die interconnects 55. It would have been obvious to the person of ordinary skill in the art before the time of filing to include the teaching of Chang for substantially greater wiring densities than the layers on the other side of the board while those layers on said other side will in turn possess lesser resistance (and greater current capacities) as taught by Chang (Abstract).
Regarding Claim 2, Jang and Chang teach the IC package of claim 1, wherein the first metallization layer is an M1 layer (can be so defined).
Regarding Claim 3, Jang and Chang teach the IC package of claim 1, wherein the second metallization layer is an M2 layer (can be so defined).
Regarding Claim 4, Jang and Chang teach the IC package of claim 1, wherein:
the plurality of die interconnects further comprise:
a third plurality of die interconnects 300c;
the substrate further comprises:
a third metallization layer 110c extending in the first direction and parallel to the second metallization layer, the third metallization layer comprising a third plurality of metal pads 120c; and
the third plurality of die interconnects extend in the second direction and terminate at the third plurality of metal pads (see Fig. 1).
Regarding Claim 5, Jang and Chang teach the IC package of claim 1, wherein:
the first metallization layer is separated by a first distance in the second direction from the second metallization layer; the first plurality of die interconnects having a first length extending in the second direction;
the second plurality of die interconnects have a second length extending in the second direction; and
the second length minus the first length is substantially equal to the first distance (H2-H1).
Regarding Claim 6, Jang and Chang teach the IC package of claim 1, but does not explicitly teach that a distance in the first direction between a metal pad of the first plurality of metal pads and a center of a die interconnect of the second plurality of die interconnects passing through the first metallization layer is in a range between 90 micrometers (um) and 120 um.
However, where the only difference between the prior art and the claims is a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device is not patentably distinct from the prior art device (MPEP 2144.04(IV)(B)).
Regarding Claim 12, Jang and Chang teach in Figs. 15-16 at least, a method for fabricating an integrated circuit (IC) package to reduce spacing requirements between die interconnects, comprising:
providing a die 200 comprising a plurality of die interconnects 300, the plurality of die interconnects comprising:
a first plurality of die interconnects 300a; and
a second plurality of die interconnects 300b;
forming a substrate, comprising:
forming a first metallization layer 100a extending in a first direction, the first metallization layer comprising a first plurality of metal pads 120a; and
forming a second metallization layer 100b extending in the first direction and parallel to the first metallization layer, the second metallization layer comprising a second plurality of metal pads 120b, wherein the first metallization layer is between the die and the second metallization layer (see Fig. 2A);
coupling the first plurality of die interconnects extending in a second direction orthogonal to the first direction to the first plurality of metal pads; and
coupling the second plurality of die interconnects extending in the second direction and through the first metallization layer to the second plurality of metal pads (see Fig. 16).
See above regarding the teaching and combination of Chang.
Regarding Claim 13, Jang and Chang teach the method of claim 12, wherein the first metallization layer is an M1 layer (can be so defined).
Regarding Claim 14, Jang and Chang teach the method of claim 12, wherein the second metallization layer is an M2 layer (can be so defined).
Regarding Claim 15, Jang and Chang teach the method of claim 12, wherein:
the plurality of die interconnects further comprise:
a third plurality of die interconnects 300c; and
forming the substrate further comprises:
forming a third metallization layer 110c extending in the first direction and parallel to the second metallization layer;
the third metallization layer comprising a third plurality of metal pads 120c;
further comprising:
coupling the third plurality of die interconnects extending in the second direction and terminating at the third plurality of metal pads (See Fig. 16).
Regarding Claim 16, Jang and Chang teach the method of claim 12, wherein:
the first metallization layer is separated by a first distance in the second direction from the second metallization layer;
the first plurality of die interconnects having a first length extending in the second direction;
the second plurality of die interconnects having a second length extending in the second direction, and
the second length minus the first length is substantially equal to the first distance (H2-H1).
Claims 7-11 and 19-21 are rejected under 35 U.S.C. 103 as being unpatentable over Jang and Chang.
Regarding Claim 7, Jang and Chang teach the IC package of claim 1, but do not explicitly teach:
the first plurality of die interconnects is interleaved between the second plurality of die interconnects so that each of the second plurality of die interconnects has at least one of the first plurality of die interconnects as a nearest neighbor in the first direction.
However, the particular placement of a claim element is an obvious matter of design choice absent showing a modification of the operation of the device (MPEP 2144.04(VI)(C)). In this case, Jang explicitly teaches that the arrangement taught is for the benefit of reducing routing space [0019]. The person of ordinary skill having the benefit of Jang may arrange the various die interconnects to meet application specific goals of integration vs. routing space.
Regarding Claims 8-10 and 17-19, Jang and Chang teach the IC package of claim 1 and method of claim 12, but does not explicitly teach: the second plurality of metal pads are coupled to ground or that the first plurality of metal pads is coupled to a power node, or a ground plane.
Jang is silent regarding the specific routing of the various metal pads, however the person of ordinary skill having the benefit of Jang can assign the pads to various I/O as applications require.
Regarding Claim 11, Jang and Chang teach the IC package of claim 1, but does not explicitly teach that it is integrated into a device selected from a group consisting of: a set top box; an entertainment unit; a navigation device; a communications device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smart phone; a session initiation protocol (SIP) phone; a tablet; a phablet; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; a vehicle component; an avionics systems; and a multicopter.
Jang is silent regarding an end application, but does mention that the device 200 may be a memory [0044], which is used in every one of the listed applications above. The person of ordinary skill having the benefit of Jang can apply it to any application as needed.
Regarding Claims 20 and 21, Jang and Chang teach the method of claim 12, but does not explicitly teach forming the first metallization layer further comprises: patterning a first photo imageable dielectric material to form a plurality of first openings in the first photo imageable dielectric material; and laminating, in the first direction, a second photo imageable dielectric material on the first photo imageable dielectric material, or patterning the second photo imageable dielectric material to form a plurality of second openings aligned with the plurality of first openings in the second direction, the plurality of first openings aligned with the plurality of second openings spanning, in the second direction, widths of the first photo imageable dielectric material and the second photo imageable dielectric material.
Jang is silent regarding the formation of openings 112a-d, but teaches forming openings through lithography elsewhere [0059-0060]. The person of ordinary skill may readily adapt the earlier teaching of Jang to form the openings as required, which would inherently take multiple lithography steps to form the various depths.
Conclusion
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/EVREN SEVEN/Primary Examiner, Art Unit 2812
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