DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restrictions
Applicant 's election without traverse of Invention I and Species A directed to Fig. 1 (claims 1-18) in the reply filed on June 22th, 2026 is acknowledged.
Claims 14-15 recites “a second ILD directly against the first liner and directly against the second liner” which describing the upper ILD 194 being the second ILD having different material from the isolation region 278 as the first liner in non-elected Species B of Fig. 9. Therefore, claims 14-15 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Species B of Fig. 9, there being no allowable generic or linking claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (Pub. No.: US 2006/0197117 A1), hereinafter as Kim.
Regarding claim 1, Kim discloses a semiconductor integrated circuit (IC) device in Fig. 2E comprising: an upper transistor (upper transistor comprising 113/115/117/125s/125d/153) comprising an upper source/drain (S/D) region (upper source 125s) with a S/D cut sidewall (sidewall of upper source 125s) (see [0026]); a lower transistor (lower transistor comprising 103/105/107/123s/123d/a portion of 101) comprising a lower S/D region (drain region 123d) (see [0022]); a first frontside contact (contact plug 157) in contact with the upper S/D region, the first frontside contact comprising a first conductive portion (material of contact plug 157) with a first cut sidewall (sidewall of contact plug 157 that directly contact layer 167a) that is substantially coplanar with the S/D cut sidewall (substantially coplanar with the sidewall of upper source 125s) (see [0029-0030]); and a second frontside contact (combination of 167a/167b/167c) in contact with the lower S/D region, the second frontside contact comprising a second conductive portion (metal plug 167c) with a second cut sidewall (sidewall of metal plug 167c that directly contact layer 167a) that faces the S/D cut sidewall and the first cut sidewall (see Fig. 2 and [0033-0034]).
Regarding claim 2, Kim discloses the semiconductor IC device of claim 1, wherein the S/D cut sidewall, the first cut sidewall, and the second cut sidewall are substantially vertical (see Fig. 2E).
Claims 1-5, 12-13 and 18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shih et al. (Patent No.: US 12,131,954 B1), hereinafter as Shih.
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Regarding claim 1, Shih discloses a semiconductor integrated circuit (IC) device in Fig.18B comprising: an upper transistor (left upper transistor 10U) comprising an upper source/drain (S/D) region (left source/drain region 62U) with a S/D cut sidewall (vertical sidewall of 62U as illustrated in annotated Fig. 18B above) (see column 8, lines 11-13 and column 6, lines 45-56); a lower transistor (right lower transistor 10L) comprising a lower S/D region (right source/drain region 62L) (see column 8, lines 11-13 and column 5, lines 56-64); a first frontside contact (contact plug 120) in contact with the upper S/D region (electrically contact), the first frontside contact comprising a first conductive portion (portion of the combination of metal region 116 and barrier/adhesion layer 114) with a first cut sidewall (sidewall of barrier/adhesion layer 114 as illustrated in annotated Fig. 18B above) that is substantially coplanar with the S/D cut sidewall (both illustrated sidewalls of barrier/adhesion layer 114 and the left source/drain region 62U are closely and approximately coplanar) (see column 11 and lines 31-39); and a second frontside contact (contact plug 118) in contact with the lower S/D region (electrically contact with the right lower source/drain region 62L), the second frontside contact comprising a second conductive portion (portion of the combination of metal region 116 and barrier/adhesion layer 114) with a second cut sidewall (sidewall of barrier/adhesion layer 114 as illustrated in annotated Fig. 18B above) that faces the S/D cut sidewall and the first cut sidewall (see column 11 and lines 31-39).
Regarding claim 2, Shih discloses the semiconductor IC device of claim 1, wherein the S/D cut sidewall, the first cut sidewall, and the second cut sidewall are substantially vertical (see annotated Fig. 18B above).
Regarding claim 3, Shih discloses the semiconductor IC device of claim 1, further comprising: an interlayer dielectric (ILD) (a combination of layer 68, 66, 70, 72, 84, 86 and 101) directly against the S/D cut sidewall, the first cut sidewall, and the second cut sidewall (see annotated Fig. 18B, column 7, lines 5-10, column 8, lines 21-30 and lines 54-62).
Regarding claim 4, Shih discloses semiconductor IC device of claim 3, wherein the ILD (the combination of layer 68, 66, 70, 72, 84, 86 and 101) is further directly against the upper S/D region, the lower S/D region, the first frontside contact, and the second frontside contact (see annotated Fig. 18B).
Regarding claim 5, Shih discloses semiconductor IC device of claim 4, wherein the first conductive portion further comprises a first opposing sidewall (the other sidewall of layer 114 of contact plug 120 as illustrated in annotated Fig. 18B above) that faces away from the second frontside contact, and wherein the second conductive portion further comprises a second opposing sidewall (the other sidewall of layer 114 of contact plug 118 as illustrated in Fig. 18B above) that faces away from the first frontside contact.
Regarding claim 12, Shih discloses a semiconductor integrated circuit (IC) device in Fig. 18A-18B comprising: an upper transistor (left upper transistor 10U) and a lower transistor (right lower transistor 10L) (see column 8, lines 11-13); a first frontside contact (contact plug 120) comprising: a first conductive portion (portion of the combination of metal region 116 and barrier/adhesion layer 114) that has a first cut sidewall (sidewall of barrier/adhesion layer 114 as illustrated in annotated Fig. 18B above) and that has a first opposing sidewall (the other sidewall of barrier/adhesion layer 114 as illustrated in annotated Fig. 18B above) that faces away from the first cut sidewall (sidewall of barrier/adhesion layer 114 as illustrated in annotated Fig. 18B above), and a first liner (left silicide layer 112U as illustrated in annotated Fig. 18B above) between the first conductive portion and the upper transistor (see Fig. 18A-18B and column 11, lines 22-39); a second frontside contact (contact plug 118) comprising: a second conductive portion (portion of the combination of metal region 116 and barrier/adhesion layer 114) that has a second cut sidewall (the other sidewall of barrier/adhesion layer 114 as illustrated in annotated Fig. 18B above) that faces the first cut sidewall and that has a second opposing sidewall that faces away from the second cut sidewall, and a second liner (right silicide layer 112L and layer 104L as illustrated in Fig. 18B above) between the second conductive portion and the lower transistor (see Figs. 18A-18B and column 11, lines 22-39, column 9, lines 36-40); and a contact cut region (portions of combination of layers 70, 72, 84, 86 and 101 between contacts 120 and 118) between the first frontside contact and the second frontside contact, the contact cut region comprising a first interlayer dielectric (ILD) directly upon the first cut sidewall and directly upon the second cut sidewall (see annotated Fig. 18B, column 7, lines 5-10, column 8, lines 21-30 and lines 54-62).
Regarding claim 13, Shih discloses the semiconductor IC device of claim 12, wherein the S/D cut sidewall, the first cut sidewall, and the second cut sidewall are substantially vertical (see annotated Fig. 18B above).
Regarding claim 18, Shih discloses the semiconductor IC device of claim 12, wherein the upper transistor comprises an upper source/drain (S/D) region (left source/drain region 62U) with a S/D cut sidewall (vertical sidewall of 62U as illustrated in annotated Fig. 18B above) that is substantially coplanar with the first cut sidewall sidewall (both illustrated sidewalls of barrier/adhesion layer 114 and the left source/drain region 62U are closely and approximately coplanar) (see annotated Fig. 18B above, column 6, lines 45-56).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
a. Determining the scope and contents of the prior art.
b. Ascertaining the differences between the prior art and the claims at issue.
c. Resolving the level of ordinary skill in the pertinent art.
d. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Shih et al. (Patent No.: US 12,131,954 B1), hereinafter as Shih, as applied to claim 12 above, and further in view of Cheng et al. (Pub. No.: US 2016/0380002 A1), hereinafter as Cheng.
Regarding claim 16, Shih discloses the semiconductor IC device of claim 12, the second liner is directly against a crystallographic plane top surface of a lower S/D region of the lower transistor (112L/104L layers directly on a crystallographic plane top surface of right lower source/drain 62L) (see annotated Fig. 18B above and column 9, lines 36-40), but fails to disclose wherein the crystallographic plane top surface of the lower S/D region of the lower transistor is (100) crystallographic plane.
Cheng discloses a semiconductor IC device comprising wherein a crystallographic plane top surface of a lower S/D region of a lower transistor (a top surface of a region of Fin 14F being contacted by third contact structure 36C/36C) is (100) crystallographic plane (layer 14 has top surface having crystal orientation of {100}) (see Fig. 4A and [0028], [0030], [0057]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention modify the crystallographic plane top surface of the lower S/D region of the lower transistor of Shih to have crystal orientation of {100} as same as the semiconductor device of Cheng because the modified device would provide a low interface states that can stabilize threshold voltage for the electrical properties of the semiconductor device and the same time having high quality and uniform material as well.
Regarding claim 17, the combination of Shih and Cheng discloses the semiconductor IC device of claim 16, wherein the second liner is further directly against one or more (111) crystallographic plane side surfaces of the lower S/D region (layer 104L of Shih directly against a vertical sidewall of right lower S/D region 62L that being modify to have crystal orientation of {100} from Cheng’s semiconductor device and the vertical sidewall of the right lower S/D region 62L would be {111} plane) (see Shih, annotated Fig. 18B above).
Allowable Subject Matter
Claims 6-11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner's statement of reasons for the indication of allowable subject matter: The cited art, whether taken singularly or in combination, especially when all limitations are considered within the claimed specific combination, fails to disclose or suggest the claimed invention having:
Further comprising: a first liner between the first opposing sidewall and the ILD and between the first conductive portion and the upper S/D region as recited in claim 6. Claims 7-11 depend on claim 6, and therefore also include said claimed limitation.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CUONG B NGUYEN whose telephone number is (571)270-1509 (Email: CuongB.Nguyen@uspto.gov). The examiner can normally be reached Monday-Friday, 8:30 AM-5:00 PM Eastern Standard Time.
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/CUONG B NGUYEN/Primary Examiner, Art Unit 2818
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