DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xu (US 2022/0013612) in view of Oh (US 2017/0317155).
[claim 19] Xu discloses a display panel (figs. 1, 2A-2B) comprising: a light emitting element (62, fig. 2A-2B, [0135]); and a pixel circuit (rest of circuit connected via electrode 61, fig. 2A) electrically connected to the light emitting element, wherein the pixel circuit includes: a buffer layer (10, fig. 2B, [0107]); a connection electrode (43/23/C2, fig. 2B); a first insulation layer (12, fig. 2B, which is the ILD isolating the electrode C2) on the buffer layer; a semiconductor pattern layer (21/41, fig. 2B, [0101]) on the first insulation layer and defining: a first semiconductor pattern (41, fig. 2B, which must be a semiconductor in order to for the transistor function) of a first transistor (T3, fig. 2B), and a second semiconductor pattern (21, fig. 2B, which must be a semiconductor in order to for the transistor function) of a second transistor (T2, fig. 2B) which is spaced apart from the first semiconductor pattern, the second semiconductor pattern electrically connected to the first semiconductor pattern by the connection electrode (fig. 2B); a second insulation layer (13, fig. 2B, [0131]) on the first insulation layer and covering the semiconductor pattern layer; a gate conductive layer (42/22, fig. 2B) on the second insulation layer and defining a first gate electrode (42, fig. 2B) of the first transistor and a second gate electrode (22, fig. 2B) of the second transistor which is spaced apart from the first gate electrode; and a third insulation layer (14, fig. 2B, [0125]) on the second insulation layer and covering the gate conductive layer; and the connection electrode includes a metal material (e.g. electrode C2 comprises metal [0134]). Xu, however, does not expressly disclose that the first/second semiconductor pattern active regions are made of polysilicon.
Oh discloses a display panel wherein the first/second semiconductor patterns (163/165, fig. 4) are made of polysilicon [0075].
It would have been obvious to one of ordinary skill in the art before the time of filing to have made Xu’s first/semiconductor patterns are made of polysilicon in order to provide a workable active region material that is commonly used, low cost, and has durable temperature tolerance.
With this modification Xu discloses:
[claim 20] The display panel of claim 19, further comprising a plurality of material layers on the buffer layer (fig. 2B), wherein the semiconductor pattern layer and the connection electrode are defined by different material layers among the plurality of material layers on the buffer layer (fig. 2B).
Allowable Subject Matter
Claims 1-18 are allowed.
The following is an examiner’s statement of reasons for allowance: A search of the prior art fails to disclose or reasonably suggest the limitations:[claim 1]” a data line on the semiconductor pattern layer and electrically connected to the second semiconductor pattern; and a connection electrode electrically connecting the first semiconductor pattern and the second semiconductor pattern which are spaced apart from each other, to each other, wherein along a thickness direction of the display panel, the connection electrode is a portion of a metal layer below the semiconductor pattern layer or a portion of a metal layer above the semiconductor pattern layer” in combination with the remaining limitations of claim 1. The nearest prior art is Xu (US 2022/0013612) but does not disclose the cited limitations.
Conclusion
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/AMAR MOVVA/Primary Examiner, Art Unit 2898
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