DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 20130266041 A1 (Giri).
Regarding claim 18: Giri teaches a method, comprising: generating a first clock signal at least by a temperature dependent resistor (clock 32, thermistor 8); generating a second clock signal at least by a temperature independent resistor (clock 32, “operational amplifier 13 has its non-inverting input line connected, through a resistor, to the output of thermistor 8 via the temperature sensor input line 9”, Paragraph [0032]; Fig. 2); generating a first digital signal and a second digital signal according to the first clock signal and the second clock signal, respectively (ADC module 20); and calculating a value of a temperature according to the first digital signal and the second digital signal (Fig. 1, PWM output signal terminal 39).
Allowable Subject Matter
Claims 1-20 allowed.
The following is an examiner’s statement of reasons for allowance:
The Examiner has identified US 20210247241 A1 (Nagata) and US 20170115725 A1 (Luo) as the references from the prior art that read best onto the claimed invention.
Nagata teaches a first resistor configured to sense a temperature (series-connection resistor 3); a first switch coupled in series with the first resistor between a first node and a second node (switch elements 3b); and a second switch coupled in parallel with the first switch (switch elements 3b).
Nagata does not teach a comparator coupled between the first node and the second node, configured to generate a first clock signal when the first switch is turned on, and configured to generate a second clock signal when the second switch is turned on; and a counter configured to generate a first digital signal according to the first clock signal, and configured to generate a second digital signal according to the second clock signal, wherein a value of the temperature is calculated at least according to the first digital signal and the second digital signal.
Luo teaches a first resistor configured to sense a temperature (thermistor 256) and a runtime system 602 to develop real-time multi-dimensional temperature compensation.
Luo does not teach a first switch coupled in series with the first resistor between a first node and a second node; a second switch coupled in parallel with the first switch; a comparator coupled between the first node and the second node; and a counter configured to generate a first digital signal according to the first clock signal, and configured to generate a second digital signal according to the second clock signal, wherein a value of the temperature is calculated at least according to the first digital signal and the second digital signal.
Therefore, neither of these references teaches the invention of independent claim 1 individually. Additionally, the Examiner believes that, since there are limitations not taught by either reference, these references combined would not teach the invention as claimed by independent claim 1.
The limitations from independent claim 1 that are missing from Nagata and Luo are also present in independent claim 12. Additionally, neither reference teaches a chop circuit as claimed in independent claim 12.
Therefore, neither Nagata nor Luo, individually or in combination, teach the limitations of independent claim 12.
Dependent claims 2-11 and 13-17 are allowable for being dependent upon an allowable base claim.
Claims 19-20 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claims 19-20 include structure found allowable in independent claims 1 and 12, but not in independent claim 18.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
JP 7329492 B2 teaches a temperature detection circuit using a temperature detection element whose resistance value changes with temperature.
JP 2023058832 A teaches a temperature measuring device with a temperature sensor and an RTD.
EP 3308115 B1 teaches an electronic temperature switch.
US 20200278261 A1 teaches a modulation circuit for voltage to duty-cycle conversion.
US 20180262000 A1 teaches a cable with a power conductor, a data conductor, and a bimetallic switch.
KR 101890333 B1 teaches a thermistor based temperature sensor having a sigma delta loop.
KR 20160050373 A teaches at least two resistors connected to at least two switches and a control unit.
KR 20160017514 A teaches a temperature-sensitive resistor, a power supply unit, and a control unit.
US 9182295 B1 teaches a temperature to digital converter circuitry to generate output data which is representative of one or more temperature dependent characteristics of a temperature sensitive device.
JP 2009053890 A teaches a resistor in series with a temperature detection element, a second resistor connected to the first in parallel with a switch.
US 20050231876 A1 teaches a power source, a signal line, a resistor, a switch, a comparator, and an overheat detecting section.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JULIA FITZPATRICK whose telephone number is (703)756-5783. The examiner can normally be reached Mon-Fri 8am-4pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Laura Martin can be reached at (571)272-2160. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JULIA FITZPATRICK/Examiner, Art Unit 2855
/LAURA MARTIN/SPE, Art Unit 2855