DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-9 in the reply filed on 04/29/2026 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-6 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cheng et al (US Pub No. 20230052084).
.
With respect to claim 1, Cheng et al discloses: an active pattern (Fig.3) comprising a lower pattern (104L) extending a first direction ( x direction) and a plurality of sheet patterns (108) spaced apart from the lower pattern in a second direction ( z direction, because it is a cross sectional view) ; a plurality of gate structures (158,126,128,156) disposed on the active pattern and comprising gate electrodes (158) extending in a third direction (in the y direction) and gate spacers (156,128,126) disposed on sidewalls of the gate electrodes (Fig.3); and a source and drain pattern (136A-B,138,140) disposed between the plurality of gate structures (Fig.3) adjacent to each other and comprising a semiconductor liner film (Para 64) and a semiconductor filling film (140) on the semiconductor liner film, wherein an uppermost sheet pattern (right next to 118) of the plurality of sheet patterns comprises an upper surface (top surface) and a bottom surface opposite to the upper surface (the bottom surface), in the second direction ( this is accordance with applicants specification), the bottom surface of the uppermost sheet pattern faces the lower pattern (bottom faces to and the left faces right), and the semiconductor liner film covers a portion of the upper surface of the uppermost sheet pattern (Fig.3).
With respect to claim 2, Cheng et al discloses, wherein the gate spacer comprises a first spacer (156) and a second spacer (126,128) the first spacer is disposed between the gate electrode and the second spacer (Fig.3), the second spacer comprises an extending portion of the second spacer extending in the third direction along the sidewall of the gate electrode (vertical portion of the 126), and a protruding portion of the second spacer (128 and bottom portion of the 126) protruding from the extending portion of the second spacer in the first direction (in the x direction), the protruding portion of the second spacer comprises a first surface facing the sheet pattern (the bottom side of 126 and 128) and a second surface opposite to the first surface of the protruding portion of the second spacer (in the y direction), and the semiconductor liner film is in contact with the first surface of the protruding portion of the second spacer (Fig.3).
With respect to claim 3, Cheng et al discloses further comprising a etch stop film (146) disposed on the source and drain pattern and in contact with the second spacer (Fig.3), wherein the etch stop film is in contact with the second surface of the protruding portion of the second spacer (the edge portion).
With respect to claim 4, Cheng et al discloses wherein a portion of the semiconductor filling film is disposed on the second surface of the protruding portion of the second spacer (it is indirectly on the second surface, applicant in their specification do not sow direct contact)
With respect to claim 5, Cheng et al discloses wherein the first spacer comprises an extending portion of the first spacer extending in the third direction along the sidewall of the gate electrode (the vertical portion), and a protruding portion of the first spacer protruding from the extending portion of the first spacer in the first direction (the horizontal portion).
With respect to claim 6, Cheng et al discloses wherein the first spacer has an I shape in a cross-sectional view (it’s vertical portion has I shape cross section).
Claim(s) 1,8 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cheng et al (US Pub No. 20230052084).
With respect to claim 1, Cheng et al discloses: an active pattern (Fig.3) comprising a lower pattern (104L) extending a first direction ( x direction) and a plurality of sheet patterns (108) spaced apart from the lower pattern in a second direction ( z direction, because it is a cross sectional view) ; a plurality of gate structures (158,126,128,156) disposed on the active pattern and comprising gate electrodes (158) extending in a third direction (in the y direction) and gate spacers (128,126) disposed on sidewalls of the gate electrodes (Fig.3); and a source and drain pattern (136A-B,138,140) disposed between the plurality of gate structures (Fig.3) adjacent to each other and comprising a semiconductor liner film (Para 64) and a semiconductor filling film (140) on the semiconductor liner film, wherein an uppermost sheet pattern (right next to 118) of the plurality of sheet patterns comprises an upper surface (top surface) and a bottom surface opposite to the upper surface (the bottom surface), in the second direction ( this is accordance with applicants specification), the bottom surface of the uppermost sheet pattern faces the lower pattern (bottom faces to and the left faces right), and the semiconductor liner film covers a portion of the upper surface of the uppermost sheet pattern (Fig.3).
With respect to claim 8, Cheng et al discloses wherein each of the plurality of gate structure comprises a gate insulating film (156) disposed between the gate spacer (126,128) and the gate electrode (Fig.3), and the gate insulating film is in contact with the semiconductor liner film (the claim does not require direct contact).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cheng et al (US Pub No. 20230052084).
With respect to claim 7, Cheng et al does not explicitly disclose wherein the first spacer has a T shape rotated by 180 degrees in a cross-sectional view. On the other hand, it would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify Cheng et al such that the first spacer has a T shape rotated by 180 degrees in a cross-sectional view as a design choice, or to increase the thickness the sidewall spacer around the gate electrode to reduce the cross talk, thereby improving the performance of the device.
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cheng et al (US Pub No. 20230052084), in view of Jeong et al (US Pub No. 20220190134).
With respect to claim 9 Cheng et al does not explicitly disclose, wherein the source and drain pattern further comprises a semiconductor insertion film disposed between the semiconductor liner film and the semiconductor filling film, and the semiconductor liner film, the semiconductor filling film, and the semiconductor insertion film comprise silicon-germanium.
However, Jeong et al discloses wherein the source and drain pattern (150,Fig.15) further comprises a semiconductor insertion film (152) disposed between the semiconductor liner film (151) and the semiconductor filling film (153,154), and the semiconductor liner film, the semiconductor filling film, and the semiconductor insertion film comprise silicon-germanium (Para 101). It would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify Cheng et al according to the teachings of the Jeon such that the source and drain pattern further comprises a semiconductor insertion film disposed between the semiconductor liner film and the semiconductor filling film, and the semiconductor liner film, the semiconductor filling film, and the semiconductor insertion film comprise silicon-germanium, in order to increase the mobility of the charges in the channel region, thereby improving the performance of the device.
Conclusion
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/ALI NARAGHI/Primary Examiner, Art Unit 2817
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