Prosecution Insights
Last updated: October 02, 2026
Application No. 18/426,040

THREE-DIMENSIONAL MEMORY DEVICE WITH COMPACT STAIRCASES AND METHODS OF FORMING THE SAME

Non-Final OA §103
Filed
Jan 29, 2024
Examiner
TRAPANESE, WILLIAM C
Art Unit
2812
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
SanDisk Technologies Inc.
OA Round
1 (Non-Final)
77%
Grant Probability
Favorable
1-2
OA Rounds
6m
Est. Remaining
98%
With Interview

Examiner Intelligence

Grants 77% — above average
77%
Career Allowance Rate
506 granted / 656 resolved
+9.1% vs TC avg
Strong +21% interview lift
Without
With
+20.9%
Interview Lift
resolved cases with interview
Typical timeline
3y 2m
Avg Prosecution
13 currently pending
Career history
669
Total Applications
across all art units

Statute-Specific Performance

§101
11.8%
-28.2% vs TC avg
§103
57.1%
+17.1% vs TC avg
§102
23.1%
-16.9% vs TC avg
§112
2.6%
-37.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 656 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of claims 1-15 in the reply filed on 06/19/2026 is acknowledged. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1, 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sun et al. (hereinafter Sun, US 2021/0296335) in view of Wang et al. (hereinafter Wang, US 2022/0270972). In regards to independent claim 1, Sun teaches a three-dimensional memory device, comprising: an alternating stack of insulating layers and electrically conductive layers, wherein the alternating stack comprises multiple staircase structures that are arranged along a first horizontal direction (Sun, [0042], Fig. 4); memory openings vertically extending through the alternating stack (Sun, [0038]); memory opening fill structures located in the memory openings, wherein each of the memory opening fill structures comprises a respective vertical stack of memory elements and a vertical semiconductor channel (Sun, [0038]); and wherein: a first subset of the memory opening fill structures is located in a first memory array region (Sun, 206-1, [0033], Fig. 2); a second subset of the memory opening fill structures is located in a second memory array region that is laterally offset from the first memory array region along a first horizontal direction (Sun, 206-2, [0033], Fig. 2); the multiple staircase structures are located in a contact region which is located between the first memory array region and the second memory array region (Sun, 406-1, 408-1/2, etc., [0044], Fig. 4); a predominant subset of the electrically conductive layers extends continuously between the first memory array region and the second memory array region within a connection region that is located between the first memory array region and the second memory array region and laterally offset from the contact region along a second horizontal direction (Sun, 404, [0044], Fig. 4); a portion of the alternating stack located in the connection region comprises connection-region taircase structures (Sun, 418-1, 418-2, [0052], Fig. 4); and each horizontally-extending surface segment within the multiple staircase structures in the contact region is vertically offset downward from a respective most proximal horizontally-extending surface segment in the connection-region staircase structures at least by a sum of a thickness of an insulating layer in the alternating stack and a thickness of an electrically conductive layer within the alternating stack (Sun, Fig. 4). Sun fails to explicitly teach at least one retro-stepped dielectric material portion contacting the multiple staircase structures. Wang teaches at least one retro-stepped dielectric material portion contacting the multiple staircase structures (Wang, [0050-0063], Fig. 1A-1D). It would have been obvious to one of ordinary skill in the art, having the teachings of Sun and Wang before him before the effective filing date of the claimed invention, to modify the three-dimensional memory device taught by Sun to include the retro-stepped dielectric of Wang in order to obtain a three-dimensional memory device with retro stepped dielectric. One would have been motivated to make such a combination because it would electrical isolate the step structures from each other. In regards to dependent claim 2, Sun teaches wherein: each staircase structure within the multiple staircase structures comprises a respective set of (K+1) horizontally-extending surface segments that are adjoined to each other by a respective set of K vertically-extending surface segments; and K is an integer greater than 2 (Sun, Fig. 4, 414-1/2). Allowable Subject Matter Claims 3-15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM C TRAPANESE whose telephone number is (571)270-3304. The examiner can normally be reached Monday - Friday 7am-12pm & 8pm-10pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached at (571)272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /WILLIAM C TRAPANESE/Primary Examiner, Art Unit 2812
Read full office action

Prosecution Timeline

Jan 29, 2024
Application Filed
Sep 22, 2026
Non-Final Rejection mailed — §103 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
77%
Grant Probability
98%
With Interview (+20.9%)
3y 2m (~6m remaining)
Median Time to Grant
Low
PTA Risk
Based on 656 resolved cases by this examiner. Grant probability derived from career allowance rate.

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