Prosecution Insights
Last updated: October 02, 2026
Application No. 18/426,069

THREE-DIMENSIONAL MEMORY DEVICE WITH COMPACT STAIRCASES AND METHODS OF FORMING THE SAME

Non-Final OA §103
Filed
Jan 29, 2024
Examiner
TRAPANESE, WILLIAM C
Art Unit
2812
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
SanDisk Technologies Inc.
OA Round
1 (Non-Final)
77%
Grant Probability
Favorable
1-2
OA Rounds
6m
Est. Remaining
98%
With Interview

Examiner Intelligence

Grants 77% — above average
77%
Career Allowance Rate
506 granted / 656 resolved
+9.1% vs TC avg
Strong +21% interview lift
Without
With
+20.9%
Interview Lift
resolved cases with interview
Typical timeline
3y 2m
Avg Prosecution
13 currently pending
Career history
669
Total Applications
across all art units

Statute-Specific Performance

§101
11.8%
-28.2% vs TC avg
§103
57.1%
+17.1% vs TC avg
§102
23.1%
-16.9% vs TC avg
§112
2.6%
-37.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 656 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of 1-15 in the reply filed on 06/26/2026 is acknowledged. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1, 5-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhang (Zhang, US 2022/0208780) in view of Wang et al. (hereinafter Wang, US 2022/0270972). In regards to independent claim 1, Zhang teaches a three-dimensional memory device, comprising: an alternating stack of insulating layers and electrically conductive layers overlying a semiconductor material layer (Zhang,, dielectric, conductive and substrate, [0040], [0050]), wherein the alternating stack comprises multiple staircase structures that are arranged along a first horizontal direction (Zhang, Fig. 7A), wherein the multiple staircase structures comprise first staircase structures that are interconnected to each other by widthwise sidewalls that laterally extend along a second horizontal direction that is perpendicular to the first horizontal direction (Zhang, 702-1, 702-2, [0102], Fig. 7A), second staircase structures that are laterally spaced from the first staircase structures, and third staircase structures that are laterally spaced from the first staircase structures and from the second staircase structures (Zhang, 702-4, [0102], Fig. 7A); memory openings vertically extending through the alternating stack ([0038]); memory opening fill structures located in the memory openings, wherein each of the memory opening fill structures comprises a respective vertical stack of memory elements and a vertical semiconductor channel (Zhang, [0038], NAND); and Zhang does not explicitly teach at least one retro-stepped dielectric material portion contacting the first staircase structures, the second staircase structures, the third staircase structures, a first surface segment of a top surface of the semiconductor material layer located between the first staircase structures and the second staircase structures, and a second surface segment of the top surface of the semiconductor material layer located between the first staircase structures and the third staircase structures. Wang teaches at least one retro-stepped dielectric material portion contacting the first staircase structures, the second staircase structures, the third staircase structures, a first surface segment of a top surface of the semiconductor material layer located between the first staircase structures and the second staircase structures, and a second surface segment of the top surface of the semiconductor material layer located between the first staircase structures and the third staircase structures (Wang, [0050-0063], Fig. 1A-1D). It would have been obvious to one of ordinary skill in the art, having the teachings of Zhang and Wang before him before the effective filing date of the claimed invention, to modify the three-dimensional memory taught by Zhang to include retro stepped dielectric material of Wang in order to obtain a three-dimensional memory with retro stepped dielectric. One would have been motivated to make such a combination because it electrically isolates the staircase structures from each other. In regards to dependent claim 5, Zhang teaches wherein the multiple staircase structures comprises: ascending staircase structures of which horizontally-extending surface segments have a stepwise-increasing height profile that increases stepwise along the first horizontal direction (Zhang, Fig. 2A, 202-2); and descending staircase structures of which horizontally-extending surface segments have a stepwise-decreasing height profile that decreases stepwise along the first horizontal direction (Zhang, Fig. 2A, 202-1). In regards to dependent claim 6, Zhang teaches: the first staircase structures comprise a laterally alternating sequence of first descending staircase structures and first ascending staircase structures that alternate along the first horizontal direction; the second staircase structures consist of a second descending staircase structure and a second ascending staircase structure; and the third staircase structures consist of a third descending staircase structure and a third ascending staircase structure (Zhang, Fig. 2A, 202-1-202-6). In regards to dependent claim 7, Zhang teaches wherein: each of the first ascending staircase structures comprises a respective set of (K+1) horizontally-extending surface segments; each of the first descending staircase structures comprises a respective set of (K+1) horizontally-extending surface segments; the second ascending staircase structure comprises a set of (K+1) horizontally-extending surface segments; and the third descending staircase structure comprises a set of (K+1) horizontally-extending surface segments (Zhang, Fig. 2A, 202-1-202-6). In regards to dependent claim 8, Zhang teaches wherein each of the first ascending staircase structures, the first descending staircase structures, the second ascending staircase structure, and the third descending staircase structure has a same lateral extent along the first horizontal direction (Zhang, Fig. 2A, 202-1-202-6). In regards to dependent claim 9, Zhang teaches: the second descending staircase structure comprises a set of (K+3) horizontally-extending surface segments; and the third ascending staircase structure comprises a set of (K+3) horizontally-extending surface segments. (Zhang, Fig. 2A, 202-1-202-6). Allowable Subject Matter Claims 2-4, and 10-15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM C TRAPANESE whose telephone number is (571)270-3304. The examiner can normally be reached Monday - Friday 7am-12pm & 8pm-10pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached at (571)272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /WILLIAM C TRAPANESE/ Primary Examiner, Art Unit 2812
Read full office action

Prosecution Timeline

Jan 29, 2024
Application Filed
Sep 22, 2026
Non-Final Rejection mailed — §103 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
77%
Grant Probability
98%
With Interview (+20.9%)
3y 2m (~6m remaining)
Median Time to Grant
Low
PTA Risk
Based on 656 resolved cases by this examiner. Grant probability derived from career allowance rate.

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