DETAILED ACTION
This Office Action is in response to the election filed on 01 June 2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of Invention I, claims 1-16 in the reply filed on 01 June 2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Claims 17-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected method, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 01 June 2026.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 2, 4, 5, 7-9, and 12 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jung (US 2017/0104019 A1; hereinafter Jung).
In regards to claim 1, Jung teaches a semiconductor device, comprising:
a first interconnect structure (238) [0115];
a device layer disposed (e.g. (122)) [0059] over the first interconnect structure (e.g. fig. 17);
a second interconnect structure (138) [0063] disposed over the device layer ((124/134) covers (122)) [0060] and comprises a topmost metallization pattern (upper most (136)) [0063];
a diamond layer (160) [0074] disposed over the second interconnect structure (fig. 20) and at least revealing a part of the topmost metallization pattern (fig. 20: (136) is exposed though an opening in (160));
a passivation layer (154) [0075] covering the diamond layer and revealing the part of the topmost metallization pattern (fig. 20: (136) is exposed through an opening in (154)); and
an electrical connector (170C1/170P1) [0118] disposed over the passivation layer and bonded to the part of the topmost metallization pattern (fig. 20: (170C1/170P1) are electrically connected to (136)) [0118].
In regards to claim 2, Jung teaches the limitations discussed above in addressing claim 1. Jung further teaches the limitations further comprising a dielectric layer (172) [0078] covering the passivation layer (e.g. (172) covers the sides of (154)) [0072] and the electrical connector bonded to the part of the topmost metallization pattern through the dielectric layer (fig. 21: (170C1) connects to (136) through (172)).
In regards to claim 4, Jung teaches the limitations discussed above in addressing claim 1. Jung further teaches the limitations further comprising a bonding film (152) [0065] disposed between the second interconnect structure and the diamond layer, wherein the bonding film revealing the part of the topmost metallization pattern (fig. 20: (136) is exposed through an opening in (152)).
In regards to claim 5, Jung teaches the limitations discussed above in addressing claim 1. Jung further teaches the limitations further comprising a carrier substrate (fig. 15: (110T)) [0146] bonded to the first interconnect structure.
In regards to claim 7, Jung teaches the limitations discussed above in addressing claim 1. Jung further teaches the limitations wherein the device structure comprises a power rail bonded to the second interconnect structure [0083].
In regards to claim 8, Jung teaches a semiconductor package, comprising:
a first die (e.g. inferred by chip (CH1)) [0104] comprising:
a device layer (fig. 20: e.g. (122)) [0059];
an interconnect structure (138/238) ([0063], [0115]) comprising a topmost metallization pattern (uppermost (136)) [0063];
a diamond layer (160)) [0074] disposed over the interconnect structure (fig. 20) and at least revealing a part of the topmost metallization pattern (fig. 20: (136) is exposed through an opening in (160)); and
a passivation layer (154) [0075] covering the diamond layer and revealing the part of the topmost metallization pattern (fig. 20: (136) is exposed through an opening in (154)); and
an encapsulating material at least laterally encapsulating the first die ([0176]: protection layer may be formed over the entire device); and
a plurality of through vias extending through the encapsulating material ([0176]: parts of the protection layer may be removed to expose conductive pad (170P1)).
In regards to claim 9, Jung teaches the limitations discussed above in addressing claim 8. Jung further teaches the limitations wherein the interconnect structure further comprises a first interconnect structure (238) [0115] and a second interconnect structure (138) [0063], the device layer (122) [0059] disposed between the first interconnect structure and the second interconnect structure (fig. 20: (122) is disposed between the top surface of (138) and the bottom surface of (238)), and the second interconnect structure comprises the topmost metallization pattern (fig. 20: the uppermost (136) is disposed in (138)).
In regards to claim 12, Jung teaches the limitations discussed above in addressing claim 9. Jung further teaches the limitations further comprising a second die (CH2) bonded to the first interconnect structure of the first die and the encapsulating material, and electrically connected to the first interconnect structure and the plurality of through vias (fig. 9).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3, 6, and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jung as applied to claims 1, 5, and 12 above.
In regards to claim 3, Jung teaches the limitations discussed above in addressing claim 1. Jung appears to be silent as to the limitation wherein a thickness of the diamond layer is substantially equal to and smaller than 20µm; however, where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. See MPEP §2144.05 II A; see also In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). In the case at hand, Jung teaches the general conditions of claim 3. Specifically, Jung teaches the limitations wherein the thickness of the diamond layer is a variable which, when changed, results in the effect of optimizing the thermal conductivity of a semiconductor device layer [0068]. Therefore, one having ordinary skill in the at the time the application at hand would find it obvious to discover the optimum or workable ranges wherein a thickness of the diamond layer is substantially equal to and smaller than 20µm using only routine skill in the art.
In regards to claim 6, Jung teaches the limitations discussed above in addressing claim 5. Jung appears to be silent as to, but does not preclude, the limitations further comprising an auxiliary diamond layer disposed between the carrier substrate and the first interconnect structure; however, Jung teaches, in a separate embodiment, the limitations of multiple heat-spreading layers (e.g. (160F1/160F2)) [0128] that can comprise diamond [0074]. It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to combine the teachings of the multiple embodiments of Jung such that an auxiliary diamond layer is disposed between the second die and the first interconnect structure to optimize the thermal conductivity of a semiconductor device layer [0068].
In regards to claim 13, Jung teaches the limitations discussed above in addressing claim 12. Jung appears to be silent as to, but does not preclude, the limitations further comprising an auxiliary diamond layer disposed between the carrier substrate and the first interconnect structure; however, Jung teaches, in a separate embodiment, the limitations of multiple heat-spreading layers (e.g. (160F1/160F2)) [0128] that can comprise diamond [0074]. It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to combine the teachings of the multiple embodiments of Jung such that an auxiliary diamond layer is disposed between the second die and the first interconnect structure to optimize the thermal conductivity of a semiconductor device layer [0068].
Claim(s) 10, 11, and 14-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jung as applied to claims 8 and 9 above, in view of Lan et al. (US 2020/0381398 A1; hereinafter Lan).
In regards to claim 10, Jung teaches the limitations discussed above in addressing claim 8. Jung appears to be silent as to, but does not preclude, the limitations further comprising a redistribution structure disposed over the first die and the encapsulating material and electrically connected to the part of the topmost metallization pattern and the plurality of through vias. Lan teaches the limitations further comprising a redistribution structure (e.g. fig. 2B: (225/RDL)) [0036] disposed over the first die (210) [0023] and the encapsulating material and electrically connected to the part of the topmost metallization pattern and the plurality of through vias. It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by Jung with the aforementioned limitations taught by Lan to route signals in a desired manner (Lan [0036]).
In regards to claim 11, the combination of Jung and Lan teaches the limitations discussed above in addressing claim 10. Lan further teaches the limitations further comprising a plurality of electrical connectors (e.g. (M4/M5/240)) [0040-0041] disposed on and electrically connected to the redistribution structure. It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by Jung with the aforementioned limitations taught by Lan to route signals in a desired manner (Lan [0036]).
In regards to claim 14, Jung teaches the limitations discussed above in addressing claim 9. Jung appears to be silent as to, but does not preclude, the limitations further comprising a redistribution structure disposed over the first interconnect structure and the encapsulating material and electrically connected to the first interconnect structure and the plurality of through vias. Lan teaches the limitations further comprising a redistribution structure (e.g. fig. 2B: (225/RDL)) [0036] disposed over the first interconnect structure and the encapsulating material and electrically connected to the first interconnect structure (e.g. (M4/M5/240)) [0040-0041] and the plurality of through vias. It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by Jung with the aforementioned limitations taught by Lan to route signals in a desired manner (Lan [0036]).
In regards to claim 15, the combination of Jung and Lan teaches the limitations discussed above in addressing claim 14. The combination of Jung and Lan appears to be silent as to, but does not preclude, the limitations further comprising an auxiliary diamond layer disposed between the carrier substrate and the first interconnect structure; however, Jung teaches, in a separate embodiment, the limitations of multiple heat-spreading layers (e.g. (160F1/160F2)) [0128] that can comprise diamond [0074]. It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to combine the teachings of the multiple embodiments of Jung such that an auxiliary diamond layer is disposed between the second die and the first interconnect structure to optimize the thermal conductivity of a semiconductor device layer [0068].
In regards to claim 16, the combination of Jung and Lan teaches the limitations discussed above in addressing claim 10. Jung further teaches the limitations further comprising a second die (CH2) disposed over the passivation layer of the first die and the encapsulating material, and electrically connected to the part of the topmost metallization pattern and the plurality of through vias (fig. 9).
Conclusion
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CALVIN CHOI
Patent Examiner
Art Unit 2812
/CALVIN Y CHOI/Primary Patent Examiner, Art Unit 2812
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