DETAILED ACTION
This Office action is in response to the application filed on 29 January 2024.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 21 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In claim 21, the recitation that “the pre-charging circuit further comprises one or more transistors” is indefinite because claim 1, from which the claim ultimately depends, already recites “a first transistor” and “a second transistor” as part of the pre-charging circuit. Based on the generic language, it appears that the first transistor and the second transistor from the independent claim 1 would necessarily be included among the “one or more transistors” recited in claim 21. This further clouds the understanding of the scope of the dependent claim, as it seems to be reciting a broader invention that does not require all of the limitations of the independent claim, as either the first or second transistor could be excluded and the pre-charge circuit would still comprise “one or more” transistors.
For purposes of examination, “one or more transistors” in claim 21 has been interpreted as at least one additional transistor.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-8, 12-14, 18, 19, 22 and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Pasotti (US 2018/0188763) in view of Tanase (U.S. Patent 6,538,496).
In re claims 1 and 23, Pasotti discloses a circuital arrangement (Figs. 3, 5A, 5B) and the corresponding method of its operation for reducing a transition phase between an inactive state and an active state of a current mirror (the method being necessarily carried out according to the functions of the circuit, as will be elucidated below), comprising:
a main current mirror (110) comprising an input leg (12) and an output leg (any of the legs 26(1)-26(n)), the input leg coupled to the output leg through a first common node (mirror node) of the main current mirror, operation of the main current mirror comprising an inactive state (see [0024]: roughly when signal ENB is active; or from in Fig. 4: the state before time t1, lasting until somewhere between t1 and t4) and an active state (see [0024]: active state is approximately the time when signal EN is active; or in Fig. 4: beginning between t1 and t4, as soon as the inactive state is considered to have ended); and
a pre-charging circuit (112) coupled to the first common node (at gate of 114 and source of 140), the pre-charging circuit comprising:
a first transistor (114) coupled to the first common node (gate of 114 coupled to mirror node), the first transistor configured to sense a voltage at the first common node during the inactive state, active state, and a transition phase from the inactive state to the active state (114 senses the voltage at the mirror node by way of its gate being directly connected thereto, which is the case throughout both states and any transition between them; see the cited circuit embodiments and see Fig. 4); and
a second transistor (140) coupled to the first common node (via its source), the second transistor configured to
Pasotti discloses the claimed invention, except that, as noted above, the second transistor is configured to sink the pre-charge current from the common node rather than source the pre-charge current to the first common node as claimed. Essentially, the difference is that Pasotti discloses a p-channel, high-side current mirror, which is a reversed-polarity counterpart to the invention disclosed in the instant application and represented by the claimed circuit, which effectively is that of an n-channel or low-side current mirror, based on the use of the term “source” as it is understood to the person of ordinary skill in the art.
As such, in the n-channel current mirror disclosed in this application and represented in the claim language, the gate capacitances on the common node are charged by sourcing the pre-charge current to raise the common node voltage and thereby speed up the turn-on of the n-channel current mirror transistors. This is contrasted with Pasotti’s p-channel circuit that, as would be understood to persons of ordinary skill in the art, requires that the gate capacitances on the common node/mirror node be discharged by sinking the pre-charge current to thereby speed up the turn-on of the p-channel current mirror transistors.
For one, Applicant admits at [0054] of the originally-filed specification that application of the current mirror concepts of one mirror polarity type to the other involves “minor circuit modifications” that are “well within the ability of a person skilled in the art”.
The admission is corroborated and confirmed to have been part of the common knowledge in the art before the effective filing date of the claimed invention by Tanase, who discloses several current mirror circuit embodiments (see Figs. 1-8), such as are frequently used in integrated circuit designs for biasing and other purposes (Col. 1, lines 5-17). These embodiments include both n-channel mirrors (e.g., Figs. 1, 3, etc.) as well as the corresponding or analogous p-channel mirrors (e.g., Figs. 2, 4, etc.).
Tanase teaches that corresponding, respective n-channel and p-channel current mirror circuits have the same effective operation and analysis, and that one may modify one configuration to produce the other by “flipping the circuit” (i.e., reversing the polarity or relative magnitudes of the supply voltages Vdd/Vss), changing the conductivity type of the transistors (from p- to n-channel or vice-versa) and reversing the current directions (see, for instance, Col. 3, lines 14-22; in other words, sourcing becomes sinking and vice-versa) in order to advantageously obtain a circuit that meets the needs of a particular device implementation.
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the current mirror circuital arrangement of Pasotti by reconfiguring it as a low-side, n-channel current mirror by performing the necessary, minor circuit modifications by flipping the circuit, changing the transistor conductivity types, and reversing the current directions, as shown and taught by Tanase, in order to enable use of the circuit in particular implementations where a load device requires the n-channel mirror arrangement over p-channel. The inevitable result of such reconfiguration would at least entail that the second transistor be configured to source the pre-charge current to the first common node in order to raise the voltage thereon to hasten activation of the main current mirror, as required by claim 1.
In re claim 3, Pasotti as reconfigured would further include wherein: a magnitude of the pre-charge current (Irsp) is different from zero only during a portion of the transition phase (Fig. 4 - the transition phase is roughly between times t1 and t3, and as shown in Fig. 4C, Irsp flows (i.e., has non-zero magnitude) only during the interval from t1 until t4, which is before the end of the transition at t3; [0033]).
In re claim 4, Pasotti as reconfigured would further include wherein: the active state (Figs. 4: after time t3) is defined by steady state voltage at the first common node (mirror node – see Fig. 4D) for a flow of a target current through the output leg ([0024]), and during the transition phase (interval from t1-t3), the pre-charge current charges (after reconfiguration to n-channel current mirror as explained above) the first common node to a pre-charge voltage that is near and below the steady state voltage (see voltage of mirror node at time t3 as shown in Fig. 4D – after the circuit is flipped or in other words the supply voltages are reversed, the mirror node voltage would be near but slightly below the steady state value at t3 instead of near and above as the figure shows).
In re claim 5, Pasotti as reconfigured would further include wherein: the first transistor (114) comprises a gate coupled to the first common node (mirror node), and the second transistor (140) comprises a source coupled to the first common node ([0026]; it is understood that this connection of the source would remain even after reconfiguration, since the NMOS 140 would become a PMOS transistor still having its source connected to the mirror node, and its drain connected to Vdd instead of ground, in order to retain the basic current mirror functionality).
In re claim 6, Pasotti as reconfigured would further include wherein: the first transistor (114) is configured as a common-source transistor (i.e., 114 as shown is understood to be a common-source configuration with the source coupled to Vdd ([0017]), and this common-source arrangement would remain true after the above reconfiguration of Pasotti, but with the common source of 114 being coupled to ground instead of Vdd), and the second transistor (140) is configured as a common-drain transistor (i.e., in an analogous manner as above, 140 is in a common-drain arrangement with its drain connected to ground, which after the reconfiguration would still be a common-drain arrangement, but with drain connected to Vdd).
In re claim 7, Pasotti as reconfigured would further include wherein: a drain of the first transistor (114) is coupled to a gate of the second transistor (140; through the optional column decoder DEC as shown in Fig. 3).
In re claim 8, Pasotti as reconfigured would further include wherein: the pre-charging circuit further comprises a current source (120a and/or 120b) coupled to the drain of the first transistor (114, through optional decoder DEC and transistor 118 as shown) and to the gate of the second transistor (140; through transistor 118 as shown).
In re claim 12, Pasotti as reconfigured would further include wherein: a size of the first transistor (114) is such that when the first common node (mirror node) is at a voltage that is equal to, or larger than, the pre-charge voltage (i.e., in Pasotti, Fig. 4 – after time t3; after the reconfiguration in view of Tanase, the common node/mirror node voltage would be rising up to and past the pre-charge voltage as explained above), a totality of a current from the current source (120a and/or 120b) flows through the first transistor ([0033] and Fig. 3).
In re claim 13, Pasotti as reconfigured would further include wherein: the size of the first transistor and sizes of transistors of the main current mirror are ratiometrically related (Pasotti: [0024]-[0025]).
In re claim 14, Pasotti as reconfigured would further include wherein: the current (Icpy) from the current source (120a/120b) and a current (Iin) that flows through the input leg (12) of the main current mirror are mirrored from a same reference current (i.e., currents Icpy and Iin are mirrored via transistors 14 and 114 from the current source 20).
In re claim 18, Pasotti as reconfigured would further include wherein: the input leg (12) comprises a diode-connected common-source transistor (14; understood to be a common-source configuration with the source coupled to Vdd; see [0017]),
the output leg (e.g., 26(1)) comprises a common-source transistor (28; coupled as a common source configuration in the same manner as explained above), and
the common-source transistor of the input leg and the common-source transistor of the output leg are ratiometrically related ([0003], [0018]).
In re claim 19, Pasotti as reconfigured would further include wherein:
a gate of the diode-connected common-source transistor (14) is tied to the first common node (mirror node), and
a gate of the common-source transistor (28) is tied to the first common node (mirror node).
In re claim 22, Pasotti as reconfigured would further include wherein: the pre-charging circuit further comprises a current source (120a and/or 120b), and the first transistor (114) is configured to drain a current (Icpy) from the current source (after flipping the circuit to an n-channel current mirror as explained above, the current sources would be connected at Vdd and 114 would be connected to ground) with a current magnitude that increases based on an increase of the volage sensed at the first common node by the first transistor ([0033] - after reconfiguring the circuit, “the decrease in the voltage at the gate (mirror) node of transistors 14 and 114” would instead involve the voltage at the mirror node increasing (Fig. 4D, flipped upside down when the supply voltages are reversed, the mirror node voltage would have an initial, steep decrease at t1, after which it would increase due to the pre-charging from the sourced current Irsp as explained previously).
Claims 9-11 are rejected under 35 U.S.C. 103 as being unpatentable over Pasotti (US 2018/0188763) and Tanase (U.S. Patent 6,538,496) as applied to claims 1, 5 and 8 above, and further in view of Klaren et al. (US 2018/0083578; hereinafter “Klaren”).
In re claim 9, Pasotti as reconfigured does not disclose wherein: the pre-charging circuit further comprises a series connected resistor coupled between the current source and the drain of the first transistor.
Whereas Klaren discloses a current mirror circuit (Fig. 7) in which a common node charging circuit (left side of figure) includes a series connected resistor (R) coupled between a current source (e.g., I_2, or I_1, or I_mirror) and the drain of a first transistor (Mb2) that is common-source connected in the current mirror. The resistor controls the gate voltage of the source-follower transistor (MSF) in order to allow an arbitrary choice of resistor values and current sources for driving the common node ([0074]-[0075]).
Therefore it would have been obvious to one of ordinary skill in the art before the claimed invention was effectively filed to have modified the current mirror from Pasotti as reconfigured in view of Tanase by further including a series connected resistor coupled between the current source and the drain of the first transistor as shown and taught by Klaren, for the stated purpose of controlling the gate voltage of the source follower in a way that allows for an arbitrary choice of resistor values and current sources for driving the common node.
In re claim 10, the above combination of Pasotti, Tanase, and Klaren would necessarily further include wherein: during the transition phase (in Pasotti, Fig. 4 – time t4-t3), a current that flows from the current source (120a/120b) through the drain of the first transistor (114) causes a voltage drop across the series connected resistor that turns ON the second transistor (i.e. Pasotti teaches that said current flow through 114 turns on transistor 140 ([0029], [0031]); after incorporating the resistor from Klaren, it would be the voltage drop across it that would at least partly control this function).
In re claim 11, the above combination of Pasotti, Tanase, and Klaren would necessarily further include wherein: when the first common node is at a voltage that is equal to, or larger than, the pre-charge voltage (i.e., in Pasotti, Fig. 4 – after time t3; after the reconfiguration in view of Tanase, the common node/mirror node voltage would be rising up to and past the pre-charge voltage as explained above), a current that flows from the current source (120a/120b) through the drain of the first transistor (114) causes a voltage drop across the series connected resistor that turns OFF the second transistor (i.e. Pasotti teaches that said current flow through 114 turns off transistor 140 ([0033]); after incorporating the resistor from Klaren, it would be the voltage drop across it that would at least partly control this function).
Claims 15-17 are rejected under 35 U.S.C. 103 as being unpatentable over Pasotti (US 2018/0188763) and Tanase (U.S. Patent 6,538,496) as applied to claim 1 above, and further in view of Ayranci et al. (U.S. Patent 10,938,349; hereinafter “Ayranci”).
In re claims 15 and 16, Pasotti as reconfigured in view of Tanase does not disclose wherein: the first transistor and the second transistor are coupled to the first common node through a series connected resistor coupled to a shunted capacitor.
Whereas Ayranci discloses a current mirror circuit (e.g., Fig. 2A) in which a bias circuit (not shown but providing VBias2) is coupled to charge a common node of the current mirror (at M2) through a series connected resistor (RB2) coupled to a shunted capacitor (CB2) in order to decouple the DC bias voltages from high frequency input and output signals in the current mirror (Col. 1, lines 43-50).
Therefore it would have been obvious to one of ordinary skill in the art before the claimed invention was effectively filed to have modified the reconfigured current mirror from Pasotti in view of Tanase such that the first transistor and the second transistor are coupled to the first common node through a series connected resistor coupled to a shunted capacitor as shown and taught by Ayranci for the stated purpose of decoupling the DC bias voltages from high frequency input and output signals in the current mirror.
In re claim 17, Pasotti as reconfigured in view of Tanase does not disclose a switching arrangement coupled to the first common node, the switching arrangement configured to short the first common node during an inactive state of the main current mirror.
Whereas Ayranci discloses a current mirror circuit (e.g., Fig. 2A) in which a switching arrangement (SW22, or all of SW21-SW23) is coupled to a common node of the current mirror (at M2) and is controlled to close and short circuit the common node to ground when the current mirror is in an inactive mode (Col. 2, lines 17-39 and Col. 6, lines 19-40) in order to maintain the main transistor OFF and allow for pre-charging of the pre-charge capacitance (CB2) for the transition phase to the next active state (Col. 6, lines 19-40).
Therefore it would have been obvious to one of ordinary skill in the art before the claimed invention was effectively filed to have modified the reconfigured current mirror from Pasotti in view of Tanase by further including a switching arrangement coupled to the first common node, the switching arrangement configured to short the first common node during an inactive state of the main current mirror as shown and taught by Ayranci, for the stated purpose of maintaining the main transistor OFF and allow for pre-charging of the pre-charge capacitance for the transition phase to the next active state.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Pasotti (US 2018/0188763) and Tanase (U.S. Patent 6,538,496) as applied to claims 1 and 18 above, and further in view of Applicant’s admitted prior art (“AAPA”; Figs. 1A-1D and [0005]-[0007] of the specification).
In re claim 18, Pasotti as reconfigured in view of Tanase does not disclose wherein: the output leg further comprises one or more cascode transistors in series connection with the common-source transistor of the output leg, the input leg further comprises one or more diode-connected transistors in series connection with the common-source transistor of the input leg, and gates of the one or more cascode transistors of the output leg are coupled to respective gates of the one or more diode-connected transistors of the input leg at respective one or more common nodes of the main current mirror.
Whereas AAPA shows a cascode configuration of a current mirror (Fig. 1B) that is well-known in the art ([0003]), and in which the output leg (110) includes one or more cascode transistors (MN11) in series connection with the common-source transistor (MN10) of the output leg, the input leg (IREF/M’N11/M’N10) further comprises one or more diode-connected transistors (M’N11) in series connection with the common-source transistor (M’N10) of the input leg, and gates of the one or more cascode transistors (MN11) of the output leg are coupled to respective gates of the one or more diode-connected transistors (M’N11) of the input leg at respective one or more common nodes of the main current mirror (N11). This cascode configuration was known to be useful in applications where the circuitry would be subject to voltages higher than the withstand voltage of the constituent transistors ([0003]).
Therefore it would have been obvious to one of ordinary skill in the art before the claimed invention was effectively filed to have modified the reconfigured current mirror from Pasotti in view of Tanase such that the output leg further comprises one or more cascode transistors in series connection with the common-source transistor of the output leg, the input leg further comprises one or more diode-connected transistors in series connection with the common-source transistor of the input leg, and gates of the one or more cascode transistors of the output leg are coupled to respective gates of the one or more diode-connected transistors of the input leg at respective one or more common nodes of the main current mirror. Such configuration was well-known in the art and would be useful in applications where the circuitry would be subject to voltages higher than the withstand voltage of the constituent transistors, as taught in AAPA.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-23 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-25 of U.S. Patent No. 11,789,481.
Although the claims at issue are not identical, they are not patentably distinct from each other because every limitation recited in claims 1-22 of the instant application is either expressly recited in one or more corresponding claims in the patent, or else is understood to be an inherent feature of those patented claims. As such, the instant claims under rejection are effectively “anticipated” by the patented claims, and thus a rejection for non-statutory double patenting is proper (see citations above).
For instance, each limitation recited by claim 1 of this application is found identically or nearly so in claim 1 of the patent, except that the instant claim 1 further specifies the first transistor as being configured to sense a voltage at the first common node during the inactive state, the active state and a transition phase from the inactive state to the active state. However, this feature is considered to be an inherent result of the functionality recited in the patented claim 1, which specifies the operation of the first transistor during each of these recited intervals and makes it clear to a person of ordinary skill in the art that the first transistor in the patented claim must be configured to sense the first common node voltage in the manner recited in the instant claim.
Claims 2-23 of the instant application all depend from claim 1, and the limitations of each of these claims may be matched to respective, corresponding limitations found in claims 1-25 of the patent.
Allowable Subject Matter
Claim 2 would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, and if a proper terminal disclaimer is filed to obviate the non-statutory double patenting rejection made above.
Claim 21 would be allowable if rewritten to overcome the rejection under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims, and further if a proper terminal disclaimer is filed to obviate the non-statutory double patenting rejection made above.
The following is a statement of reasons for the indication of allowable subject matter:
With respect to claim 2, the prior art of record does not disclose or suggest the circuital arrangement in which, “during the inactive state, a voltage at the first common node is about zero volts and the first transistor is turned OFF,” in combination with all of the remaining features required by claim 2.
With respect to claim 21, under the interpretations provided above in this Office action, the prior art of record fails to disclose or to suggest the one or more [additional] transistors in the pre-charge circuit, being coupled to the one or more additional common nodes and being configured to source a pre-charge current to respective nodes based on the voltage sensed at the first common node by the first transistor, in combination with all of the remaining features as required by claim 21.
Conclusion
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/FRED E FINCH III/Primary Examiner, Art Unit 2838