Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objection
Claim 15 is objected for claim language “…. the plurality of through wafer trenches to form to form a plurality of deep trench isolations and a plurality fo through-wafer isolations……”.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the 20claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3 are rejected under 35 U.S.C. 103 as being unpatentable over
Mishra et al. (US 2009/0261448, hereinafter Mishra) in view of Wang (US 2003/0139010, hereinafter Wang).
With respect to claim 1, Mishra discloses a semiconductor device (Fig. 3e), comprising: a substrate (310); a plurality of active regions (para 0015 – active areas) that are disposed on the substrate (para 0015); a plurality of first type of trench isolations having a first top critical dimension (CD) (narrower trenches), each of the plurality of the first type of trench isolations including sidewalls that taper towards one another along a depth direction (narrower trenches have tapered sidewall along a depth direction); and a plurality of second type of trench isolations having a second top CD (wider trenches – it’s obvious there will be more than one wider trench), the second top CD being larger than the first top CD (second top critical dimensions are bigger for wider trenches than narrower trenches) and each of the plurality of the second type of trench isolations having a flat bottom trench surface (bottom of the wider trench is flat).
Mishra does not explicitly disclose that the active regions are parallelly aligned.
In an analogous art, Wang discloses that the active regions are parallelly aligned (Para 0014-0015; 0018). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Mishra’s method/system by having Wang’s disclosure in order to maximize packaging density and simplify manufacturing of a semiconductor device.
With respect to claim 2, Mishra discloses the plurality of second type of trench isolations are disposed adjacent to edges of each of the plurality of active regions (Para 0015).
Mishra does not explicitly disclose wherein the plurality of first type of trench isolations are disposed adjacent to channel regions of each of the plurality of active regions.
In an analogous art, Wang discloses wherein the plurality of first type of trench isolations are disposed adjacent to channel regions of each of the plurality of active regions (Para 0016-0019). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Mishra’s method/system by having Wang’s disclosure in order to maximize packaging density and simplify manufacturing of a semiconductor device.
With respect to claim 3, Mishra discloses wherein the plurality of first type of trench isolations and the plurality of second type of trench isolations each has a sidewall slope angle that is measured from an upper surface of corresponding trench isolation and that ranges from 85 degrees to 90 degrees (Para 0018 and 0028).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over
Mishra/Wang in view of Marty et al. (US 2004/0147093, hereinafter Marty).
With respect to claim 4, Mishra/Wang discloses the semiconductor device of claim 3.
Mishra discloses wherein the first top CD of the plurality of first type of trench isolations ranges from 50nm to 100nm, the second top CD of the plurality of second type of trench isolations ranges from 50nm to 300nm (Para 0004 and 0016).
Mishra/Wang does not explicitly disclose that the plurality of first type of trench isolations and the plurality of second type of trench isolations have a trench depth ranging from 750nm to 2000nm.
In an analogous art, Marty discloses that the plurality of first type of trench isolations and the plurality of second type of trench isolations have a trench depth ranging from 750nm to 2000nm (Para 0012 – depth 1 micrometer). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Mishra/Wang’s method/system by having Marty’s disclosure in order to isolate different components of a semiconductor device.
Claim 5-8 are rejected under 35 U.S.C. 103 as being unpatentable over
Mishra/Wang in view of Bartray (CN 104752337, hereinafter Bartray).
With respect to claim 5, Mishra/Wang does not explicitly disclose wherein the plurality of second type of trench isolations pass through the substrate.
In an analogous art, Bartray discloses wherein the plurality of second type of trench isolations pass through the substrate (Page 05; para 01-02 – holes through the substrate). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Mishra/Wang’s method/system by having Bartray’s disclosure in order to connect different components of a semiconductor device.
With respect to claim 6, Mishra/Wang does not explicitly disclose a plurality of through-wafer interconnects passing through corresponding second type of trench isolations, the plurality of through-wafer interconnects being connected to corresponding local word line (LWL) contacts disposed above the plurality of active regions.
In an analogous art, Bartray discloses a plurality of through-wafer interconnects passing through corresponding second type of trench isolations (Page 05; Para 01-02), the plurality of through-wafer interconnects being connected to corresponding local word line (LWL) contacts disposed above the plurality of active regions (Page 15; Para 02; Page 17; Para 03 – local word line). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Mishra/Wang’s method/system by having Bartray’s disclosure in order to connect different components of a semiconductor device.
With respect to claim 7, Mishra/Wang does not explicitly disclose wherein the semiconductor device is bonded to a memory module, and wherein the plurality of through-wafer interconnects are connected to corresponding array wafer landing pads of the memory module, respectively.
In an analogous art, Bartray discloses wherein the semiconductor device is bonded to a memory module (Page 10; Para 03), and wherein the plurality of through-wafer interconnects are connected to corresponding array wafer landing pads of the memory module, respectively (Page 10; Para 02-03). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Mishra/Wang’s method/system by having Bartray’s disclosure in order to connect different components of a semiconductor device.
With respect to claim 8, Mishra does not explicitly disclose a plurality of ion implanted regions that are disposed under corresponding first type trench isolations, wherein the sidewall of the first type trench isolations is segmented.
In an analogous art, Wang discloses a plurality of ion implanted regions that are disposed under corresponding first type trench isolations (Para 0079; 0087; 0090 – ion implantation), wherein the sidewall of the first type trench isolations is segmented (Fig. 3H). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Mishra’s method/system by having Wang’s disclosure in order to maximize packaging density and simplify manufacturing of a semiconductor device.
Claims 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over
Chen et al. (US 2021/0013088, hereinafter Chen) in view of Wang and further in view of Lin et al. (US 2012/0193785, hereinafter Lin).
With respect to claim 9, Chen discloses a semiconductor device (Fig. 9), comprising: a complementary metal-oxide-semiconductor (CMOS) device (Para 0047; 0060 and 0111 – CMOS devices) including a substrate and a plurality of string driver devices (Fig. 1B; Para 0051 – memory strings), each of the plurality of string driver devices including: a plurality of active regions (Para 0060, 0072-0073– active regions) that are disposed on the substrate (Fig. 1B), each of the plurality of active regions includes one or more channel regions (Para 0051; 0053; and 0088– channel region), a plurality of deep trench isolations (Fig. 8; Para 0107 – isolation trenches 894), each of the plurality of the deep trench isolations including sidewalls that taper towards one another along a depth direction (Fig. 8- sidewalls of 894 tapered), and a memory device including one or more memory arrays (Para 0047 – memory arrays); wherein the CMOS device is bonded to the memory device (Para 0047).
Chen does not explicitly disclose that the active regions are parallelly aligned; and the deep trench isolations are disposed adjacent to the channel regions of the plurality of active regions.
In an analogous art, Wang discloses that the active regions are parallelly aligned (Para 0014-0015; 0018); and the deep trench isolations are disposed adjacent to the channel regions of the plurality of active regions (Para 0016-0019). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Mishra’s method/system by having Wang’s disclosure in order to maximize packaging density and simplify manufacturing of a semiconductor device.
Chen/Wang does not explicitly disclose a plurality of through-wafer isolations (TWIs) that are disposed adjacent to corresponding edges of the plurality of active regions; and having the plurality of TWIs of the CMOS device connected to the memory device (Para 0060).
In an analogous art, Lin discloses a plurality of through-wafer isolations (TWIs) (Para 0131; 0164; and 0179 – vias pass through more than one wafer) that are disposed adjacent to corresponding edges of the plurality of active regions (Para 0119); having the plurality of TWIs of the CMOS device connected to the memory device (Para 0210 -0211). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Cheng/Wang’s method/system by having Lin’s disclosure in order to connect different components of a semiconductor device.
With respect to claim 10, Cheng/Wang does not explicitly disclose wherein the plurality of TWIs have a flat bottom trench surface and pass through the substrate.
In an analogous art, Lin discloses wherein the plurality of TWIs have a flat bottom trench surface and pass through the substrate (Para 0095; Fig. 29 -thorough vias 77 have flat bottom trench).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Cheng/Wang’s method/system by having Lin’s disclosure in order to connect different components of a semiconductor device.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over
Chen/Wang/Lin and further in view of Mishra.
With respect to claim 11, Cheng/Wang does not explicitly disclose wherein the plurality of first type of trench isolations and the plurality of second type of trench isolations each has a sidewall slope angle that is measured from an upper surface of corresponding trench isolation and that ranges from 85 degrees to 90 degrees.
In an analogous art, Mishra discloses wherein the plurality of first type of trench isolations and the plurality of second type of trench isolations each has a sidewall slope angle that is measured from an upper surface of corresponding trench isolation and that ranges from 85 degrees to 90 degrees (Para 0018 and 0028). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Cheng/Wang/Lin’s method/system by having Mishra’s disclosure in order to reduce void formation in a semiconductor device.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over
Chen/Wang/Lin/Mishra and further in view of Marty.
With respect to claim 12, Mishra/Wang/Lin/Mishra discloses the semiconductor device of claim 11.
Mishra discloses wherein the first top CD of the plurality of first type of trench isolations ranges from 50nm to 100nm, the second top CD of the plurality of second type of trench isolations ranges from 50nm to 300nm (Para 0004 and 0016).
Chen/Wang/Lin/Mishra does not explicitly disclose that the plurality of first type of trench isolations and the plurality of second type of trench isolations have a trench depth ranging from 750nm to 2000nm.
In an analogous art, Marty discloses that the plurality of first type of trench isolations and the plurality of second type of trench isolations have a trench depth ranging from 750nm to 2000nm (Para 0012 – depth 1 micrometer). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Chen/Wang/Lin/Mishra’s method/system by having Marty’s disclosure in order to isolate different components of a semiconductor device.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over
Chen/Wang/Lin and further in view of Bartray.
With respect to claim 13, Mishra/Wang/Lin does not explicitly disclose a plurality of through- wafer interconnects passing through corresponding TWI, the plurality of through-wafer interconnects being connected to corresponding local word line (LWL) contacts disposed above the plurality of active regions of the CMOS device, wherein the plurality of through- wafer interconnects are connected, through corresponding TWIs, to corresponding memory arrays of the memory device.
In an analogous art, Bartray discloses a plurality of through-wafer interconnects passing through corresponding TWI (Page 05; Para 01-02), the plurality of through-wafer interconnects being connected to corresponding local word line (LWL) contacts disposed above the plurality of active regions of the CMOS device (Page 10; Para 01), wherein the plurality of through- wafer interconnects are connected, through corresponding TWIs (Page 09; Para 03), to corresponding memory arrays of the memory device (Page 15; Para 02; Page 17; Para 03 – local word line). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Mishra/Wang/Lin’s method/system by having Bartray’s disclosure in order to connect different components of a semiconductor device.
Claims 14 is rejected under 35 U.S.C. 103 as being unpatentable over
Chen/Wang/Lin in view of Edwards et al. (US 2009/0159967, hereinafter Edwards).
With respect to claim 14, Chen/Wang/Lin discloses the semiconductor device of claim 9.
Chen/Wang/Lin does not explicitly disclose wherein each of the plurality of active regions is wider under corresponding channels included therein, compared to its remaining region.
In an analogous art, Edwards discloses wherein each of the plurality of active regions is wider under corresponding channels included therein, compared to its remaining region (Para 0021; 0026-0027). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Mishra/Wang/Lin’s method/system by having Edward’s disclosure in order to produce more powerful semiconductor devices.
Claims 15 is rejected under 35 U.S.C. 103 as being unpatentable over
Lin in view of Wang.
With respect to claim 15, Lin discloses a method of forming a string driver device (Para 0056), comprising:
providing a complementary metal-oxide-semiconductor (CMOS) wafer (Para 0048; 0152; CMOS) including a plurality of active regions (Para 0092; and 0119) that are parallelly aligned, the semiconductor wafer having a plurality of small opening regions (6a of Fig. 20 – Para 0082 – shallow trenches) and a plurality of large opening regions on its frontside surface (4a of Fig. 20 - Para 0083 -deep trenches); etching the CMOS wafer, through the plurality of small opening regions and the plurality of large opening regions, to form a plurality of deep trenches that extend into the CMOS wafer by a first depth and a plurality of through-wafer trenches that extend into the CMOS wafer by a second depth greater than the first depth, respectively (Fig. 20A - Para 0083, 0086-0087 – deep trenches extends more in depth than shallow trenches); depositing dielectric materials (5 of Fig. 21) into the plurality of deep trenches and the plurality of through wafer trenches to form a plurality of deep trench isolations (Fig. 54)and a plurality of through-wafer isolations (TWIs), respectively ( Para 0119; 0131; 0164; and 0179 – vias pass through more than one wafer); and thinning the CMOS wafer from its backside surface to expose the plurality of TWIs (Para 0126; 0160; Fig. 78-79).
Lin does not explicitly disclose that the active regions are parallelly aligned.
In an analogous art, Wang discloses that the active regions are parallelly aligned (Para 0014-0015; 0018). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Lin’s method/system by having Wang’s disclosure in order to maximize packaging density and simplify manufacturing of a semiconductor device.
Claims 16 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Lin/Wang in view of Mishra.
With respect to claim 16, Lin discloses that each of the plurality of the through wafer trenches has a flat bottom trench surface (Fig. 31).
Lin/Wang does not explicitly disclose that wherein each of the plurality of deep trenches includes sidewalls that taper towards one another along a depth direction.
In an analogous art, Mishra discloses that wherein each of the plurality of deep trenches includes sidewalls that taper towards one another along a depth direction (Fig. 3e -tapered sidewalls).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Lin/Wang’s method/system by having Mishra’s disclosure in order to improve electrical field.
With respect to claim 20, Lin/Wang does not explicitly disclose wherein etching the CMOS wafer to form the plurality of deep trenches and the plurality of through wafer trenches includes turning an etch angle from 85 degrees to 90 degrees.
In an analogous art, Mishra discloses wherein etching the CMOS wafer to form the plurality of deep trenches and the plurality of through wafer trenches includes turning an etch angle from 85 degrees to 90 degrees (Para 0018 and 0028). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Cheng/Wang/Lin’s method/system by having Mishra’s disclosure in order to reduce void formation in a semiconductor device.
Allowable Subject Matter
Claim 17 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
With respect to claim 17, none of the prior art on record disclose or render obvious the claimed limitations including “etching through the plurality of small opening regions until a third depth to form flat trench bottom surface, the third depth being less than the first depth of the plurality of deep trenches, depositing a spacer layer on sidewall and the bottom surface of each of the plurality of deep trenches, removing the spacer layer from the bottom surface of each of the plurality of deep trenches,
etching, through the plurality of small opening regions and the bottom surface of
each of the plurality of deep trenches, until the plurality of deep trenches reach the first
depth target, ion implanting into the plurality of deep trenches to form ion implanted regions there below, and removing the spacer layer from the plurality of deep trenches” when considered as a whole along with all of the limitations of the base claim and any intervening claims.
Claims 18-19 have been objected because of their dependency on claim 17.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMAD M CHOUDHRY whose telephone number is (571)270-5716. The examiner can normally be reached Monday - Friday.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Fairbanks Brent can be reached at 408-918-7532. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MOHAMMAD M CHOUDHRY/Primary Examiner, Art Unit 2899
Prosecution Insights