Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claims 1, 3-12, 14, add 16-20 have been considered but are moot because the arguments do not apply to any of the references being used in the current rejection.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made
Claims 1, 3-12, 14, 16, 20, and 22-26 are rejected under 35 U.S.C. 103 as being unpatentable over Meixner (US 2016/0313984, hereinafter Meixner) in view of Eyole et al. (US 2022/0391214, hereinafter Eyole).
Regarding claim 1, Meixner discloses
A processor-implemented method for parallel processing comprising:
accessing an array of compute elements, wherein each compute element within the array of compute elements (paragraph [0045]: the virtualized environment can be viewed as a type of two-dimensional (2D), SIMD processor composed of a 2D array of, e.g., identical processors each executing identical code in lock-step) is known to a compiler (paragraph [0037]: FIG. 1 shows a high level view of an image processor technology platform that includes a virtual image processing environment 101, the actual image processing hardware 103 and a compiler 102 for translating higher level code written for the virtual processing environment 101 to object code that the actual hardware 103 physically executes) and is coupled to its neighboring compute elements within the array of compute elements (paragraph [0127]: the pair of execution lanes 1110 are drawn as horizontal neighbors when in fact, according to the following example, they are vertical neighbors);
providing control for the compute elements on a cycle-by-cycle basis, wherein control is enabled by a stream of wide control words generated by the compiler (paragraph [0113]: the instruction format of the instructions read from scalar memory 903 and issued to the execution lanes of the execution lane array 905 includes a very-long-instruction-word (VLIW) type format that includes more than one opcode per instruction; paragraph [0119]: the execution of the VLIW word includes a first cycle upon which the scalar instruction 951 is executed followed by a second cycle upon with the other instructions 952, 953 may be executed (note that in various embodiments instructions 952 and 953 may be executed in parallel);
managing data to be stored by the array of compute elements, wherein the data to be stored is targeted to a data cache coupled to the array of compute elements (paragraph [0167]: Given that the execution lane array is intended to operate in a SIMD like fashion, the program code will naturally cause execution lanes in the array (which includes both rows and columns) to issue memory access requests on a same cycle), and wherein the managing includes detecting and mitigating memory hazards (paragraph [0167]: competing memory access from execution lane s on a same row is a foreseeable hazard; paragraph [0168]: In the example of FIG. 22, note that the final object code 2202 includes a sequence of four sequential memory load instructions across four cycles to ensure that the memory access of one execution lane does not interfere with the memory access of another execution lane along the same row);
examining pending data cache accesses for hazards, wherein the examining comprises a store probe (paragraph [0167]: Given that the execution lane array is intended to operate in a SIMD like fashion, the program code will naturally cause execution lanes in the array (which includes both rows and columns) to issue memory access requests on a same cycle. Thus, competing memory access from execution lanes on a same row is a foreseeable hazard. FIG. 22 shows a pair of threads 2201 for execution on two different execution lanes on a same row. Given the SIMD-like nature of the machine both execution lanes execute same opcodes in same cycles including a pair of memory load instructions in the first two depicted cycles. Examining the addresses of the memory load instructions, note that all the addresses are different); and
committing store data to the data cache, wherein the committing is based on a result of the store probe (paragraph [0168]: As such, when the compiler imposes a memory load instruction into the object code it also recognizes that memory load instructions will impose conflicts for execution lanes that reside on a same row. In response, the compiler will impose sequential memory load instructions into the code to effectively unroll the competing memory load instruction along a same row so that each execution lane is provided with its own reserved cycle for accessing the memory. In the example of FIG. 22, note that the final object code 2202 includes a sequence of four sequential memory load instructions across four cycles to ensure that the memory access of one execution lane does not interfere with the memory access of another execution lane along the same row).
Meixner does not disclose coupling access buffers between the array of compute elements and the data cache; identifying hazardous loads and stores by comparing load and store addresses to addresses of contents of the access buffer, wherein the comparing is based on precedence information that includes hardware ordering of data cache access loads to the array of compute elements and data cache access stores from the array of compute elements, wherein the precedence information is augmented at run time.
Eyole discloses coupling access buffers between the array of compute elements and the data cache (paragraph [0044]: This internal buffer between the access and execute parts is managed by hardware and is transparent to software; paragraph [0075]: Data values returned from the cache/memory hierarchy are passed to the decoupled access buffer); identifying hazardous loads and stores by comparing load and store addresses to addresses of contents of the access buffer (paragraph [0074]: Updates which could cause a data hazard (i.e. a collision between a younger load and an older store) are identified, such that remedial action can be taken and this feature is discussed in more detail with reference to FIG. 5 below; paragraph [0077]: The collision detection circuitry 312 is arranged to monitor the respective content of the store unit 316 and the decoupled access buffer 311 and to identify instances in which the address matches between entries. This may for example be carried out by a circular (looping) examination of the entries of one of them, e.g. the DAB 311, taking the address of each entry in turn and checking if there is a matching entry in the other, e.g. the store unit 316. When a pair of addresses are found to match then the respective ordering of the corresponding instructions is determined with reference to the ROB IDs, and when a data hazard is thus identified (a “collision”) the collision detection circuitry causes a flush to be carried out; paragraph [0078]: when there is a matching address the flow proceeds to step 402, where it is determined if the store unit entry precedes (in program order) the load which has caused the value to be brought into the decoupled access buffer (DAB). If this is not the case then the flow returns to step 400 for the next entry of the decoupled access buffer to be examined. If, however, this is the case, then a collision condition has been identified and at step 403 the load instruction itself is squashed and any subsequent instructions in the access and execute circuitry are flushed in order to avoid incorrect side-effects of the ordering of the load and store operations having been inverted), wherein the comparing is based on precedence information that includes hardware ordering of data cache access loads to the array of compute elements and data cache access stores from the array of compute elements, wherein the precedence information is augmented at run time (paragraph [0077]: Various information associated may be associated with each entry, though of relevance to the present discussion (as shown in the example of FIG. 6) this information comprises the value to be stored, the address at which it is to be stored, and an instruction identifier (which here is provided by a reorder buffer (ROB) ID. The decoupled access buffer 311 also comprises various information related to the entries which it holds, which in the example of FIG. 6 is shown to be an address of the retrieved value, the value itself, and an instruction identifier associated with this load operation, which in the example of FIG. 6 is also the ROB ID … It is known to one of ordinary skill in the art that out-of-order execution pipelines such as those provided by the access circuitry 210 and the execute circuitry 220 of the example of FIG. 4 make use of such a re-order buffer and ROB IDs, in order to maintain knowledge of the program ordering of the instructions which they execute, such that despite the out-of-order execution they carry out, the effect of the instructions can be correctly ordered when the results are committed; In this case, The ROB IDs are assigned dynamically during instruction issue and execution, meaning the precedence/order information is implicitly augmented at run time as instructions are dispatched and executed out-of-order). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teaching of Meixner by incorporating Eyole’s decoupled access buffer and collision-detection/store-probe mechanism — i.e., a DAB combined with store-buffer comparisons using an address-matching scheme, ROB-ID based ordering checks, and gated commits to the L1 data cache. The motivation would have been to positioning decoupled access buffer advantageously close to the point at which its content is required (e.g. the execute instruction execution circuitry), thus not only reducing latency by bringing data closer to the CPU, but also improving access bandwidth to said data (Eyole paragraph [0045]).
Regarding claim 25 referring to claim 1, Meixner discloses A computer program product embodied in a non-transitory computer readable medium for parallel processing, the computer program product comprising code which causes one or more processors to perform operations of: … (Fig. 24, paragraph [0195]).
Regarding claim 26 referring to claim 1, Meixner discloses A computer system for parallel processing comprising: a memory which stores instructions; one or more processors coupled to the memory, wherein the one or more processors, when executing the instructions which are stored, are configured to: … (Fig. 24, paragraph [0195]).
Regarding claim 3, Meixner discloses
wherein the access buffers are coupled to the array of compute elements through a crossbar switch (paragraph [0095]: As observed in FIG. 7, the architecture 700 includes a plurality of line buffer units 701_1 through 701_M interconnected to a plurality of stencil processor units 702_1 through 702_N and corresponding sheet generator units 703_1 through 703_N through a network 704 (e.g., a network on chip (NOC) including an on chip switch network, an on chip ring network or other kind of network)).
Regarding claim 4, Meixner discloses
wherein the pending data cache accesses are examined in the access buffer (paragraph [0095]: The image processor may be targeted, for example, by a compiler that converts program code written for a virtual processor within a simulated environment into program code that is actually executed by the hardware processor. As observed in FIG. 7, the architecture 700 includes a plurality of line buffer units 701_1 through 701_M interconnected to a plurality of stencil processor units 702_1 through 702_N and corresponding sheet generator units 703_1 through 703_N through a network 704 (e.g., a network on chip (NOC) including an on chip switch network, an on chip ring network or other kind of network); paragraph [0167]: Examining the addresses of the memory load instructions, note that all the addresses are different; paragraph [0168]: As such, when the compiler imposes a memory load instruction into the object code it also recognizes that memory load instructions will impose conflicts for execution lanes that reside on a same row).
Regarding claim 5, Meixner discloses
wherein the examining comprises interrogating the access buffer for pending load or store addresses (paragraph [0095]: The image processor may be targeted, for example, by a compiler that converts program code written for a virtual processor within a simulated environment into program code that is actually executed by the hardware processor. As observed in FIG. 7, the architecture 700 includes a plurality of line buffer units 701_1 through 701_M interconnected to a plurality of stencil processor units 702_1 through 702_N and corresponding sheet generator units 703_1 through 703_N through a network 704 (e.g., a network on chip (NOC) including an on chip switch network, an on chip ring network or other kind of network); paragraph [0167]: Examining the addresses of the memory load instructions, note that all the addresses are different; paragraph [0168]: As such, when the compiler imposes a memory load instruction into the object code it also recognizes that memory load instructions will impose conflicts for execution lanes that reside on a same row).
Regarding claim 6, Meixner discloses
wherein the interrogating compares a store probe address to the pending load or store addresses (paragraph [0167]: Examining the addresses of the memory load instructions, note that all the addresses are different).
Regarding claim 7, Meixner discloses
wherein the store probe address is not associated with a data field (paragraph [0167]: Examining the addresses of the memory load instructions, note that all the addresses are different).
Regarding claim 8, Meixner discloses
wherein the access buffers hold load data for the array of compute elements (paragraph [0100]: In the case of an image processing pipeline or a DAG flow having a single input, generally, input frames are directed to the same line buffer unit 701_1 which parses the image data into line groups and directs the line groups to the sheet generator 703_1 whose corresponding stencil processor 702_1 is executing the code of the first kernel in the pipeline/DAG; paragraph [0165]: n these circumstances the compiler will insert memory load or memory store instructions into the object code (as opposed to register load or register store instructions) to fetch/write data from/to random access memory rather than register space).
Regarding claim 9, Meixner discloses
wherein the load data is being held for hazard detection and mitigation (paragraph [0095]: The image processor may be targeted, for example, by a compiler that converts program code written for a virtual processor within a simulated environment into program code that is actually executed by the hardware processor. As observed in FIG. 7, the architecture 700 includes a plurality of line buffer units 701_1 through 701_M interconnected to a plurality of stencil processor units 702_1 through 702_N and corresponding sheet generator units 703_1 through 703_N through a network 704 (e.g., a network on chip (NOC) including an on chip switch network, an on chip ring network or other kind of network); paragraph [0167]: competing memory access from execution lane s on a same row is a foreseeable hazard … Examining the addresses of the memory load instructions, note that all the addresses are different; paragraph [0168]: As such, when the compiler imposes a memory load instruction into the object code it also recognizes that memory load instructions will impose conflicts for execution lanes that reside on a same row … In the example of FIG. 22, note that the final object code 2202 includes a sequence of four sequential memory load instructions across four cycles to ensure that the memory access of one execution lane does not interfere with the memory access of another execution lane along the same row).
Regarding claim 10, Meixner discloses
wherein a result of the store probe indicating no hazard detection (paragraph [0166]: when two different execution lanes on different rows execute a memory load instruction during a same cycle the instructions are not competing because they are directed to different random access memories; paragraph [0167]: Examining the addresses of the memory load instructions, note that all the addresses are different) enables data transfer from the access buffers to the array of compute elements (paragraph [0100]: In the case of an image processing pipeline or a DAG flow having a single input, generally, input frames are directed to the same line buffer unit 701_1 which parses the image data into line groups and directs the line groups to the sheet generator 703_1 whose corresponding stencil processor 702_1 is executing the code of the first kernel in the pipeline/DAG).
Regarding claim 11, Meixner discloses
wherein the access buffers hold data (paragraph [0100]: In the case of an image processing pipeline or a DAG flow having a single input, generally, input frames are directed to the same line buffer unit 701_1 which parses the image data into line groups and directs the line groups to the sheet generator 703_1 whose corresponding stencil processor 702_1 is executing the code of the first kernel in the pipeline/DAG) awaiting commitment to the data cache (paragraph [0168]: As such, when the compiler imposes a memory load instruction into the object code it also recognizes that memory load instructions will impose conflicts for execution lanes that reside on a same row. In response, the compiler will impose sequential memory load instructions into the code to effectively unroll the competing memory load instruction along a same row so that each execution lane is provided with its own reserved cycle for accessing the memory. In the example of FIG. 22, note that the final object code 2202 includes a sequence of four sequential memory load instructions across four cycles to ensure that the memory access of one execution lane does not interfere with the memory access of another execution lane along the same row).
Regarding claim 12, Meixner discloses
wherein a result of the store probe indicating no pending data awaiting commitment (paragraph [0166]: when two different execution lanes on different rows execute a memory load instruction during a same cycle the instructions are not competing because they are directed to different random access memories; paragraph [0167]: Examining the addresses of the memory load instructions, note that all the addresses are different) enables data transfer from the access buffers to the array of compute elements (paragraph [0100]: In the case of an image processing pipeline or a DAG flow having a single input, generally, input frames are directed to the same line buffer unit 701_1 which parses the image data into line groups and directs the line groups to the sheet generator 703_1 whose corresponding stencil processor 702_1 is executing the code of the first kernel in the pipeline/DAG).
Regarding claim 14, Meixner discloses wherein the comparing identifies potential accesses to the same address. Eyole does not disclose wherein the comparing identifies potential accesses to the same address (paragraph [0074]: Updates which could cause a data hazard (i.e. a collision between a younger load and an older store) are identified, such that remedial action can be taken and this feature is discussed in more detail with reference to FIG. 5 below; paragraph [0077]: The collision detection circuitry 312 is arranged to monitor the respective content of the store unit 316 and the decoupled access buffer 311 and to identify instances in which the address matches between entries. This may for example be carried out by a circular (looping) examination of the entries of one of them, e.g. the DAB 311, taking the address of each entry in turn and checking if there is a matching entry in the other, e.g. the store unit 316. When a pair of addresses are found to match then the respective ordering of the corresponding instructions is determined with reference to the ROB IDs, and when a data hazard is thus identified (a “collision”) the collision detection circuitry causes a flush to be carried out; paragraph [0078]: when there is a matching address the flow proceeds to step 402, where it is determined if the store unit entry precedes (in program order) the load which has caused the value to be brought into the decoupled access buffer (DAB). If this is not the case then the flow returns to step 400 for the next entry of the decoupled access buffer to be examined. If, however, this is the case, then a collision condition has been identified and at step 403 the load instruction itself is squashed and any subsequent instructions in the access and execute circuitry are flushed in order to avoid incorrect side-effects of the ordering of the load and store operations having been inverted). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teaching of Meixner by incorporating Eyole’s decoupled access buffer and collision-detection/store-probe mechanism — i.e., a DAB combined with store-buffer comparisons using an address-matching scheme, ROB-ID based ordering checks, and gated commits to the L1 data cache. The motivation would have been to positioning decoupled access buffer advantageously close to the point at which its content is required (e.g. the execute instruction execution circuitry), thus not only reducing latency by bringing data closer to the CPU, but also improving access bandwidth to said data (Eyole paragraph [0045]).
Regarding claim 16, Meixner discloses further comprising delaying promoting data to the access buffer and/or releasing data from the access buffer. Eyole does not disclose further comprising delaying promoting data to the access buffer and/or releasing data from the access buffer (paragraph [0077]: The collision detection circuitry 312 is arranged to monitor the respective content of the store unit 316 and the decoupled access buffer 311 and to identify instances in which the address matches between entries. This may for example be carried out by a circular (looping) examination of the entries of one of them, e.g. the DAB 311, taking the address of each entry in turn and checking if there is a matching entry in the other, e.g. the store unit 316. When a pair of addresses are found to match then the respective ordering of the corresponding instructions is determined with reference to the ROB IDs, and when a data hazard is thus identified (a “collision”) the collision detection circuitry causes a flush to be carried out. This flush may be a full pipeline flush or may be a partial pipeline flush). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teaching of Meixner by incorporating Eyole’s flushing data from DAB when data hazard is idenfied. The motivation would have been to positioning decoupled access buffer advantageously close to the point at which its content is required (e.g. the execute instruction execution circuitry), thus not only reducing latency by bringing data closer to the CPU, but also improving access bandwidth to said data (Eyole paragraph [0045]).
Regarding claim 20, Meixner discloses wherein the identifying enables hazard mitigation. Eyole does not disclose wherein the identifying enables hazard mitigation (paragraph [0074]: Updates which could cause a data hazard (i.e. a collision between a younger load and an older store) are identified, such that remedial action can be taken and this feature is discussed in more detail with reference to FIG. 5 below; paragraph [0077]: The collision detection circuitry 312 is arranged to monitor the respective content of the store unit 316 and the decoupled access buffer 311 and to identify instances in which the address matches between entries. This may for example be carried out by a circular (looping) examination of the entries of one of them, e.g. the DAB 311, taking the address of each entry in turn and checking if there is a matching entry in the other, e.g. the store unit 316. When a pair of addresses are found to match then the respective ordering of the corresponding instructions is determined with reference to the ROB IDs, and when a data hazard is thus identified (a “collision”) the collision detection circuitry causes a flush to be carried out; paragraph [0078]: when there is a matching address the flow proceeds to step 402, where it is determined if the store unit entry precedes (in program order) the load which has caused the value to be brought into the decoupled access buffer (DAB). If this is not the case then the flow returns to step 400 for the next entry of the decoupled access buffer to be examined. If, however, this is the case, then a collision condition has been identified and at step 403 the load instruction itself is squashed and any subsequent instructions in the access and execute circuitry are flushed in order to avoid incorrect side-effects of the ordering of the load and store operations having been inverted). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teaching of Meixner by incorporating Eyole’s remedial action when hazard is identified. The motivation would have been to positioning decoupled access buffer advantageously close to the point at which its content is required (e.g. the execute instruction execution circuitry), thus not only reducing latency by bringing data closer to the CPU, but also improving access bandwidth to said data (Eyole paragraph [0045]).
Regarding claim 22, Meixner discloses
wherein the examining occurs in logic coupling the array of compute elements to the data cache (paragraph [0100]: In the case of an image processing pipeline or a DAG flow having a single input, generally, input frames are directed to the same line buffer unit 701_1 which parses the image data into line groups and directs the line groups to the sheet generator 703_1 whose corresponding stencil processor 702_1 is executing the code of the first kernel in the pipeline/DAG ; paragraph [0166]: when two different execution lanes on different rows execute a memory load instruction during a same cycle the instructions are not competing because they are directed to different random access memories; paragraph [0167]: Examining the addresses of the memory load instructions, note that all the addresses are different).
Regarding claim 23, Meixner discloses
wherein the compiler provides static scheduling for the array of compute elements (paragraph [0059]: it is expected that SIMD image processing sequences will often perform a look-up into a same look-up table during a same clock cycle. When confronted with virtual code having inefficient data access sequences from a two-dimensional shift array perspective, the compiler will reorder the data access sequence to keep the number of shifts minimal between mathematical operations (e.g., one shift between mathematical operations)).
Regarding claim 24, Meixner discloses
wherein the wide control words are variable length control words (paragraph [0113]: the instruction format of the instructions read from scalar memory 903 and issued to the execution lanes of the execution lane array 905 includes a very-long-instruction-word (VLIW) type format that includes more than one opcode per instruction; paragraph [0119]: the execution of the VLIW word includes a first cycle upon which the scalar instruction 951 is executed followed by a second cycle upon with the other instructions 952, 953 may be executed (note that in various embodiments instructions 952 and 953 may be executed in parallel)).
Claims 17 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Meixner (US 2016/0313984, hereinafter Meixner) in view of Eyole et al. (US 2022/0391214, hereinafter Eyole) as applied to claim 1, and further in view of Larri et al. (US 2023/0259605, hereinafter Larri).
Regarding claim 17, Meixner in view of Eyole does not disclose wherein the delaying avoids hazards. Larri discloses wherein the delaying avoids hazards (paragraph [0096]: The buffer 208 may be a buffer already provided in the data processing apparatus for preventing ordering hazards between load and store instructions, and includes an address field 604 for storing an address in memory at which an authentication code is to be stored (which might be in the stack); paragraph [0098]: if a subsequent instruction is a load or store instruction, its target address may be compared with the address fields 604 in the buffer 208 whose corresponding valid bits 606 indicate that the address field is valid. If the target address matches a valid address stored in the buffer 208, processing of the subsequent instruction may be stalled until the authentication code is available (e.g. stored in the data field 608 or stored to the stack). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teaching of Meixner in view of Eyole by comparing the target address with the address fields in the buffer if a subsequent instruction is a load or store instruction for preventing ordering hazards between load and store instructions and stalling processing of the subsequent instruction if the target address matches a valid address stored in the buffer of Larri. The motivation would have been to prevent ordering hazards between load and store instructions (Larri paragraph [0096]).
Regarding claim 18, Meixner in view of Eyole does not disclose wherein the avoiding hazards is based on a comparative precedence value. Larri discloses wherein the avoiding hazards is based on a comparative precedence value (paragraph [0096]: The buffer 208 may be a buffer already provided in the data processing apparatus for preventing ordering hazards between load and store instructions, and includes an address field 604 for storing an address in memory at which an authentication code is to be stored (which might be in the stack); paragraph [0098]: if a subsequent instruction is a load or store instruction, its target address may be compared with the address fields 604 in the buffer 208 whose corresponding valid bits 606 indicate that the address field is valid. If the target address matches a valid address stored in the buffer 208, processing of the subsequent instruction may be stalled until the authentication code is available (e.g. stored in the data field 608 or stored to the stack). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teaching of Meixner in view of Eyole by comparing the target address with the address fields in the buffer if a subsequent instruction is a load or store instruction for preventing ordering hazards between load and store instructions and stalling processing of the subsequent instruction if the target address matches a valid address stored in the buffer of Larri. The motivation would have been to prevent ordering hazards between load and store instructions (Larri paragraph [0096]).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Meixner (US 2016/0313984, hereinafter Meixner) in view of Eyole et al. (US 2022/0391214, hereinafter Eyole) as applied to claim 1, and further in view of Kothinti Naresh (US 2020/0310814, hereinafter Kothinti Naresh).
Regarding claim 19, Meixner in view of Eyole does not disclose wherein the hazardous loads and stores include write-after-read conflicts, read-after-write conflicts, and write-after-write conflicts. Kothinti Naresh does not disclose wherein the hazardous loads and stores include write-after-read conflicts (paragraph [0042]: A write-after-read (WAR) hazard may arise when a younger store instruction executes earlier than an older load instruction to the same address and the younger store instruction overwrites data cache 210, for example, before the older load instruction reads the correct data), read-after-write conflicts (paragraph [0038] A read-after-write (RAW) hazard may arise when a younger (in program order) load instruction executes earlier than an older store instruction to the same address, which results in the load instruction getting stale data from data cache 210), and write-after-write conflicts (paragraph [0043]: A write-after-write (WAW) hazard may arise when a younger store instruction executes earlier than an older store instruction to the same address, resulting in data cache 210 having a stale value (produced by the older store instruction, instead of the younger store instruction)). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teaching of Meixner in view of Eyole by resolve WAR, RAW, WAW hazards which may arise due to out-of-order execution and memory ordering techniques of Kothinti Naresh. The motivation would have been to resolve data hazards which may arise due to out-of-order execution and memory ordering techniques (Kothinti Naresh paragraph [0037]).
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Meixner (US 2016/0313984, hereinafter Meixner) in view of Eyole et al. (US 2022/0391214, hereinafter Eyole) as applied to claim 20, and further in view of Bryant et al. (US 2017/0293567, hereinafter Bryant).
Regarding claim 21, Meixner in view of Eyole does not disclose wherein the hazard mitigation includes load-to-store forwarding, store-to-load forwarding, and store-to-store forwarding. Bryant discloses wherein the hazard mitigation includes load-to-store forwarding (paragraph [0081]: The comparison performed by the checking circuitry could be for a number of purposes, e.g. any of the load-to-load, store-to-store or load-to-store hazard checking described above), store-to-load forwarding (paragraph [0052]: Store-to-load hazarding circuitry 130 is provided for detecting whether any hazard conditions occur between store transactions pending in the store buffer 40 and load transactions pending in the load buffer 120), and store-to-store forwarding (paragraph [0046]: The store-to-store hazard checking circuitry 70 performs hazard checking between the new store transaction and any pending store transaction in a valid transaction slot 42 of the store buffer). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teaching of Meixner in view of Eyole by performing comparison by checking circuitry e.g., load-to-load, store-to-store, store-to-load, or load-to-store hazard of Bryant. The motivation would have been to ensure that a series of data access transactions to the same location in the data store are handled in the correct order (Bryant paragraph [0003]).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in [0037] CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to [0037] CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SISLEY N. KIM whose telephone number is (571)270-7832. The examiner can normally be reached M-F 11:30AM -7:30PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, April Y. Blair can be reached on (571)270-1014. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SISLEY N KIM/Primary Examiner, Art Unit 2196 09/26/2025