DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 – 3, 5, 7, 9, 11, 13, 15 – 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over ARISAKA et al. (US 20170141023 A1, “ARISAKA”) in view of Lin et al. (US 20070023919 A1, “Lin”) and Yamasaki (US 20090200072 A1, “Yamasaki”)
Regarding claim 1, ARISAKA discloses (Fig. 1A, 5B & 6A) a printed wiring board (10), comprising: a conductor layer (40); an outermost insulating layer (42) formed on the conductor layer (40) such that the outermost insulating layer has an opening (42x) exposing a portion of the conductor layer (See para [0034]); and a metal post (50) formed in the opening of in the outermost insulating layer and comprising a seed layer (60) and an electrolytic plating layer (51+52) formed on the seed layer such that the metal post has a height exceeding a surface of the outermost insulating layer and has a portion exceeding a height of the outermost insulating layer (See Fig. 6A), wherein the seed layer of the metal post has a first layer comprising copper (61) and a second layer (62) formed on the first layer such that the metal post includes the first layer (61), the second layer comprising copper (62), and the electrolytic plating layer (51+52), and the portion of the metal post exceeding the height of the outermost insulating layer is formed such that a width of the first layer is larger than a width of the second layer (See Fig. 6A), and
ARISAKA is silent on a width of the electrolytic plating layer is larger than the width of the first layer.
However, Lin discloses (Fig. 1) a width of the electrolytic plating layer (20) is larger than the width of the first layer (18) (See para [0033]).
ARISAKA and Lin are both considered to be analogous to the claimed invention because they are in the same field of wiring substrate. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified ARISAKA to incorporate the teachings of Lin and provide a width of the electrolytic plating layer (20) is larger than the width of the first layer (18) (See para [0033]). Doing so would enhance mechanical reliability, relief stress and prevent cracks (A person skilled in the art knows that a rigid connection transfers stress, while a relieved structure (like an undercut), can absorb it)
ARISAKA in view of Lin is silent on a first seed layer comprising copper.
However, Yamasaki discloses (Fig. 9) a first seed layer (15) comprising copper (See para [0085]).
ARISAKA in view of Lin and Yamasaki are both considered to be analogous to the claimed invention because they are in the same field of Wiring Board. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified ARISAKA in view of Lin to incorporate the teachings of Yamasaki and provide a first seed layer (15) comprising copper (See para [0085]). Doing so would improve the bonding strength from peeling from the insulating layer (para [0090]).
Regarding claim 2, ARISAKA in view of Lin and Yamasaki discloses the printed wiring board according to claim 1, wherein ARISAKA further discloses that the metal post is formed such that the seed layer is formed by sputtering (See para [0042] & [0076]).
Regarding claim 3, ARISAKA in view of Lin and Yamasaki discloses the printed wiring board according to claim 1, Yamasaki further discloses wherein the seed layer of the metal post is formed such that the first layer (15) and the second layer (16) are a combination of copper alloys of different materials or a combination of the copper alloys and copper (See para [0093] – [0095]).
Regarding claim 5, ARISAKA in view of Lin and Yamasaki discloses the printed wiring board according to claim 3, wherein Yamasaki further discloses that the metal post is formed such that the first layer (15) of the seed layer includes a copper alloy comprising at least one of silicon, aluminum, titanium, nickel, chromium, iron, molybdenum, silver, carbon, oxygen, tin, calcium and magnesium and that the second layer of the seed layer (16) includes copper (See para [0093] – [0095]).
Regarding claim 7, ARISAKA in view of Lin and Yamasaki discloses the printed wiring board according to claim 1, wherein ARISAKA further discloses the metal post is formed such that the first layer of the seed layer includes at least one of aluminum, titanium, nickel, chromium, calcium, magnesium, iron, molybdenum and silver and that the second layer of the seed layer includes copper (See para [0042], [0076]).
Regarding claim 9, ARISAKA in view of Lin and Yamasaki discloses the printed wiring board according to claim 2, Yamasaki further discloses wherein the seed layer of the metal post is formed such that the first layer and the second layer are a combination of copper alloys of different materials or a combination of the copper alloys and copper (See para [0093] – [0095]).
Regarding claim 11, ARISAKA in view of Lin and Yamasaki the printed wiring board according to claim 9, wherein Yamasaki further discloses that the metal post is formed such that the first layer (15) of the seed layer includes a copper alloy comprising at least one of silicon, aluminum, titanium, nickel, chromium, iron, molybdenum, silver, carbon, oxygen, tin, calcium and magnesium and that the second layer (16) of the seed layer includes copper (See para [0093] – [0095]).
Regarding claim 13, ARISAKA in view of Lin and Yamasaki discloses the printed wiring board according to claim 2, wherein ARISAKA further discloses the metal post is formed such that the first layer of the seed layer includes at least one of aluminum, titanium, nickel, chromium, calcium, magnesium, iron, molybdenum and silver and that the second layer of the seed layer includes copper (See para [0042], [0076]).
Regarding claim 15, ARISAKA in view of Lin and Yamasaki discloses the printed wiring board according to claim 1, wherein the seed layer of the metal post is formed such that the first layer (See Yamasaki first seed layer) and the second layer (ARISAKA discloses that the second seed layer (62) is a copper alloy which inherently includes copper and at least 1 other material) are a combination of copper alloys of different materials.
Regarding claim 16, ARISAKA in view of Lin and Yamasaki discloses the printed wiring board according to claim 1, wherein Yamasaki discloses the seed layer of the metal post is formed such that the first layer (15) and the second layer (16) are a combination of the copper alloys and copper (See para [0093] – [0095]).
Regarding claim 17, ARISAKA in view of Lin and Yamasaki discloses the printed wiring board according to claim 1, wherein the seed layer of the metal post is formed such that the first layer (See Yamasaki first seed layer) and the second layer (ARISAKA discloses that the second seed layer (62) is a copper alloy which inherently includes copper and at least 1 other material) are a combination of copper alloys of different materials.
Regarding claim 18, ARISAKA in view of Lin and Yamasaki discloses the printed wiring board according to claim 2, wherein Yamasaki further discloses the seed layer of the metal post is formed such that the first layer and the second layer are a combination of the copper alloys and copper (See para [0093] – [0095]).
Claim(s) 4, 10 and 19 – 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over ARISAKA et al. (US 20170141023 A1, “ARISAKA”) in view of Lin et al. (US 20070023919 A1, “Lin”) and Yamasaki (US 20090200072 A1, “Yamasaki”) as applied to claim 3, 9, 15 and 17 above, and further in view of Chung et al. (US 20030057526 A1, “Chung”)
Regarding claim 4, ARISAKA in view of Lin and Yamasaki discloses the printed wiring board according to claim 3,
ARISAKA in view of Lin and Yamasaki is silent on wherein the seed layer of the metal post is formed such that the copper alloys have a copper content of 90% or more of a total weight
However, Chung discloses (Fig. 5A-C) wherein the seed layer of the metal post is formed such that the copper alloys have a copper content of 90% or more of a total weight (See para [0061]).
ARISAKA in view of Lin, Yamasaki and Chung are both considered to be analogous to the claimed invention because they are in the same field of wiring board. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified ARISAKA in view of Lin and Yamasaki to incorporate the teachings of Chung and provide wherein the seed layer of the metal post is formed such that the copper alloys have a copper content of 90% or more of a total weight (See para [0061]). Doing so would provide excellent electrical and high thermal conductivity (See para [0061]).
Regarding claim 10, ARISAKA in view of Lin and Yamasaki discloses the printed wiring board according to claim 9,
ARISAKA in view of Lin and Yamasaki is silent on wherein the seed layer of the metal post is formed such that the copper alloys have a copper content of 90% or more of a total weight
However, Chung discloses (Fig. 5A-C) wherein the seed layer of the metal post is formed such that the copper alloys have a copper content of 90% or more of a total weight (See para [0061]).
ARISAKA in view of Lin, Yamasaki and Chung are both considered to be analogous to the claimed invention because they are in the same field of wiring board. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified ARISAKA in view of Lin and Yamasaki to incorporate the teachings of Chung and provide wherein the seed layer of the metal post is formed such that the copper alloys have a copper content of 90% or more of a total weight (See para [0061]). Doing so would provide excellent electrical and high thermal conductivity (See para [0061]).
Regarding claim 19, ARISAKA in view of Lin and Yamasaki discloses the printed wiring board according to claim 15,
ARISAKA in view of Lin and Yamasaki is silent on wherein the seed layer of the metal post is formed such that the copper alloys have a copper content of 90% or more of a total weight
However, Chung discloses (Fig. 5A-C) wherein the seed layer of the metal post is formed such that the copper alloys have a copper content of 90% or more of a total weight (See para [0061]).
ARISAKA in view of Lin, Yamasaki and Chung are both considered to be analogous to the claimed invention because they are in the same field of wiring board. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified ARISAKA in view of Lin and Yamasaki to incorporate the teachings of Chung and provide wherein the seed layer of the metal post is formed such that the copper alloys have a copper content of 90% or more of a total weight (See para [0061]). Doing so would provide excellent electrical and high thermal conductivity (See para [0061]).
Regarding claim 20, ARISAKA in view of Lin and Yamasaki discloses the printed wiring board according to claim 17,
ARISAKA in view of Lin and Yamasaki is silent on wherein the seed layer of the metal post is formed such that the copper alloys have a copper content of 90% or more of a total weight
However, Chung discloses (Fig. 5A-C) wherein the seed layer of the metal post is formed such that the copper alloys have a copper content of 90% or more of a total weight (See para [0061]).
ARISAKA in view of Lin, Yamasaki and Chung are both considered to be analogous to the claimed invention because they are in the same field of wiring board. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified ARISAKA in view of Lin and Yamasaki to incorporate the teachings of Chung and provide wherein the seed layer of the metal post is formed such that the copper alloys have a copper content of 90% or more of a total weight (See para [0061]). Doing so would provide excellent electrical and high thermal conductivity (See para [0061]).
Claim(s) 6 and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over ARISAKA et al. (US 20170141023 A1, “ARISAKA”) in view of Lin et al. (US 20070023919 A1, “Lin”) and Yamasaki (US 20090200072 A1, “Yamasaki”) as applied to claim 5 & 11 above, and further in view of Chang et al. (US 20120292768 A1, “Chang”)
Regarding claim 6, ARISAKA in view of Lin and Yamasaki discloses the printed wiring board according to claim 5, wherein the metal post is formed such that
ARISAKA in view of Lin and Yamasaki is silent on the first layer of the seed layer includes a copper alloy comprising aluminum and silicon.
However, Chang discloses (Fig. 2G) the first layer of the seed layer includes a copper alloy comprising aluminum and silicon (See Claims 7, 16 and 20).
ARISAKA in view of Lin, Yamasaki and Chang are both considered to be analogous to the claimed invention because they are in the same field of wiring board. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified ARISAKA in view of Lin, Yamasaki to incorporate the teachings of Chang and provide the first layer of the seed layer includes a copper alloy comprising aluminum and silicon (See Claims 7, 16 and 20). Doing so would improve the electromigration resistance of the structure which is critical for the long-term reliability.
Regarding claim 12, ARISAKA in view of Lin and Yamasaki discloses the printed wiring board according to claim 11, wherein the metal post is formed such that
ARISAKA in view of Lin and Yamasaki is silent on the first layer of the seed layer includes a copper alloy comprising aluminum and silicon.
However, Chang discloses (Fig. 2G) the first layer of the seed layer includes a copper alloy comprising aluminum and silicon (See Claims 7, 16 and 20).
ARISAKA in view of Lin, Yamasaki and Chang are both considered to be analogous to the claimed invention because they are in the same field of wiring board. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified ARISAKA in view of Lin and Yamasaki to incorporate the teachings of Chang and provide the first layer of the seed layer includes a copper alloy comprising aluminum and silicon (See Claims 7, 16 and 20). Doing so would improve the electromigration resistance of the structure which is critical for the long-term reliability.
Claim(s) 8 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over ARISAKA et al. (US 20170141023 A1, “ARISAKA”) in view of Lin et al. (US 20070023919 A1, “Lin”) and Yamasaki (US 20090200072 A1, “Yamasaki”) as applied to claim 1 & 2 above, and further in view of TERAUCHI (US 20200163214 A1, “TERAUCHI”)
Regarding claim 8, ARISAKA in view of Lin and Yamasaki discloses the printed wiring board according to claim 1,
ARISAKA in view of Lin and Yamasaki is silent on wherein the metal post is formed such that a first angle between a side surface of the seed layer and the surface of the outermost insulating layer is larger than a second angle between the surface of the outermost insulating layer and a straight line from a lower edge of a side surface of the electrolytic plating layer toward a boundary portion between the seed layer and the electrolytic plating layer.
However, TERAUCHI discloses (Fig. 8) wherein the metal post (22e) is formed such that a first angle between a side surface of the seed layer (25) and the surface of the outermost insulating layer (12) is larger than a second angle between the surface of the outermost insulating layer and a straight line from a lower edge of a side surface of the electrolytic plating layer toward a boundary portion between the seed layer and the electrolytic plating layer (See annotated figure below).
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ARISAKA in view of Lin, Yamasaki and TERAUCHI are both considered to be analogous to the claimed invention because they are in the same field of wiring board. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified ARISAKA in view of Lin and Yamasaki to incorporate the teachings of TERAUCHI and provide wherein the metal post (22e) is formed such that a first angle between a side surface of the seed layer (25) and the surface of the outermost insulating layer (12) is larger than a second angle between the surface of the outermost insulating layer and a straight line from a lower edge of a side surface of the electrolytic plating layer toward a boundary portion between the seed layer and the electrolytic plating layer (See annotated figure below). Doing so would ensure an optimal distribution of the plating material. The wider top of the plating provides extra provides extra metal volume at the top where it is needed most.
Regarding claim 14, ARISAKA in view of Lin and Yamasaki discloses the printed wiring board according to claim 2,
ARISAKA in view of Lin and Yamasaki is silent on wherein the metal post is formed such that a first angle between a side surface of the seed layer and the surface of the outermost insulating layer is larger than a second angle between the surface of the outermost insulating layer and a straight line from a lower edge of a side surface of the electrolytic plating layer toward a boundary portion between the seed layer and the electrolytic plating layer.
However, TERAUCHI discloses (Fig. 8) wherein the metal post (22e) is formed such that a first angle between a side surface of the seed layer (25) and the surface of the outermost insulating layer (12) is larger than a second angle between the surface of the outermost insulating layer and a straight line from a lower edge of a side surface of the electrolytic plating layer toward a boundary portion between the seed layer and the electrolytic plating layer (See annotated figure below).
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media_image1.png
517
967
media_image1.png
Greyscale
ARISAKA in view of Lin, Yamasaki and TERAUCHI are both considered to be analogous to the claimed invention because they are in the same field of wiring board. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified ARISAKA in view of Lin and Yamasaki to incorporate the teachings of TERAUCHI and provide wherein the metal post (22e) is formed such that a first angle between a side surface of the seed layer (25) and the surface of the outermost insulating layer (12) is larger than a second angle between the surface of the outermost insulating layer and a straight line from a lower edge of a side surface of the electrolytic plating layer toward a boundary portion between the seed layer and the electrolytic plating layer (See annotated figure below). Doing so would ensure an optimal distribution of the plating material. The wider top of the plating provides extra provides extra metal volume at the top where it is needed most.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SIDI MOHAMED MAIGA whose telephone number is (703)756-1870. The examiner can normally be reached Monday - Friday 8 am 5 pm.
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/SIDI M MAIGA/
Examiner, Art Unit 2847
/TIMOTHY J THOMPSON/Supervisory Patent Examiner, Art Unit 2847
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