DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of the restriction requirement in the reply filed on 5/20/26 is acknowledged. The traversal is on the ground(s) that the there is no burden on the examiner and that the requirements for restriction have not been established. This is not found persuasive because, as noted in the restriction requirement, “In the instant case, the product of Invention I as claimed can be made by another and materially different process than that of Invention II as claimed, namely one in which the raised interconnect layer and dielectric layer are formed prior to the disposition of the IC die”. Thus, the requirement is clearly met. Additionally, the Examiner established both “the inventions require a different field of search (e.g., searching different classes/subclasses or electronic resources/employing different search queries) and the prior art applicable to one invention would not likely be applicable to the other invention,” thus the argument that there is no search burden is not persuasive.
The requirement is still deemed proper and is therefore made FINAL.
Claims 17-20 withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected invention, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 5/20/26.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-6, 9-13, and 16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Fang et al. (US Patent Application Publication No. 2022/0310488) (“Fang”).
Regarding Claim 1, Fang teaches a substrate comprising: a surface interconnect layer comprising a plurality of surface interconnects (Figure 3, item 122) extending between a first area (Figure 3, item 122a) and a second area (Figure 3, item 222b) on a first surface, the first area configured to couple to an integrated circuit (IC) die (Figure 3, item 103); a dielectric layer (Figure 3, item 140) disposed on the surface interconnect layer in the second area; and a raised interconnect layer (Figure 3, item 223b) disposed on the dielectric layer and comprising a plurality of raised interconnects (see Figure 10D, items on right side exposed through item 14) coupled to the plurality of surface interconnects through the dielectric layer (see profile view of Figure 2 and item 223b/222b).
Regarding Claim 2, Fang further teaches the plurality of surface interconnects comprises a first surface interconnect extending from a first location in the second area to a second location in the second area (see profile view of Figure 2 and item 223b/222b); and the plurality of raised interconnects comprise a first raised interconnect coupled to the first surface interconnect in the first location and in the second location (see profile view of Figure 2 and item 223b/222b).
Regarding Claim 3, Fang further teaches a first via extending through the dielectric layer to couple the first surface interconnect to the first raised interconnect in the first location (Figure 3, item 122i); and a second via extending through the dielectric layer to couple the first surface interconnect to the first raised interconnect in the second location (see Figure 10D).
Regarding Claim 4, Fang further teaches the second area is on a perimeter of the first area (see Figure 3).
Regarding Claim 5, Fang further teaches he first surface further comprising a third area between the second area and an edge of the substrate, wherein the dielectric layer is not disposed in the third area (see Figure 12, note gaps in 140 on right side).
Regarding Claim 6, Fang further teaches the dielectric layer extends from the perimeter of the first area to an edge of the substrate (see Figure 3, note location of item 140 on far edge).
Regarding Claim 9, Fang further teaches a first center-to-center distance between two adjacent surface interconnects of the plurality of surface interconnects in the first area is greater than a second center-to-center distance between the two adjacent surface interconnects in the second area (see Figure 12, note spacing distances on left side around 112a vs spacing in center around 122b).
Regarding Claim 10, Fang further teaches a first width of the first surface interconnect of the plurality of surface interconnects in the first area is greater than a second width of the first surface interconnect in the second area (note this claim does not require the entire width of a top surface of the interconnect to be measured and compared to each element, thus a smaller width is chosen for 122a vs 122b to meet the claim language).
Regarding Claim 11, Fang further teaches a package comprising:a first integrated circuit (IC) die (Figure 3, item 103) disposed in a first area of a first surface of a package substrate; a surface interconnect layer (Figure 3, item 122e) comprising a plurality of surface interconnects coupled to the first IC die and extending to a second area of the first surface of the package substrate; a dielectric layer (Figure 3, item 140) disposed on the surface interconnect layer in the second area of the package substrate; and a raised interconnect layer (Figure 3, item 223b) disposed on the dielectric layer and comprising a plurality of raised interconnects coupled to the plurality of surface interconnects (Figure 3, item 222b – see also exploded view in Figure 2) through the dielectric layer.
Regarding Claim 12, Fang further teaches the plurality of surface interconnects comprises a first surface interconnect extending from a first location in the second area to a second location in the second area (see profile view of Figure 2 and item 223b/222b); and the plurality of raised interconnects comprise a first raised interconnect coupled to the first surface interconnect in the first location and in the second location (see profile view of Figure 2 and item 223b/222b).
Regarding Claim 13, Fang further teaches the raised interconnect layer further comprising package contacts on the dielectric layer and electrically coupled to the plurality of raised interconnects coupled to the first IC die (see Figure 3).
Regarding Claim 16, Fang further teaches the package of claim 11 integrated into a device selected from the group consisting of: a set-top box; an entertainment unit; a navigation device; a communications device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smartphone; a session initiation protocol (SIP) phone; a tablet; a phablet; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; a vehicle component; an avionics system; a drone; and a multicopter (¶0095).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 7, 8, 14, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Fang as applied to Claims 2 or 13 above, and further in view of Lee et al. (US Patent Application Publication No. 2020/0066613) (“Lee”).
Regarding Claim 7, Fang teaches Claim 2 as indicated above. Fang does not specifically teach the raised interconnect layer further comprising package contacts coupled to the plurality of raised interconnects and configured to couple to package interconnects further coupled to a second substrate. However, Lee teaches including a second substrate (Figure 21, item 180, ¶0075) connected to a lower raised contact (Figure 21,item 113b) via a package contact (Figure 21, items 113a+113c). It would have been obvious to a person having ordinary skill in art at the time of effective filing to use the teachings of Lee to include the additional substrate and contacts into the device of Fang, as doing so would increase package density within the same footprint, thus allowing for more functionality in the same size package.
Regarding Claim 8, Lee further teaches one of the package contacts is disposed in the second location (see Figure 21).
Regarding Claim 14, Fang teaches Claim 13 as indicated above. Fang does not specifically teach a second substrate coupled to the package contacts on the dielectric layer, the first IC die disposed between the package substrate and the second substrate. However, Lee teaches including a second substrate (Figure 21, item 180, ¶0075) connected to a lower raised contact (Figure 21,item 113b) via a package contact (Figure 21, items 113a+113c) where an IC chip (Figure 21, item 121) is between the substrates (see Figure 21). It would have been obvious to a person having ordinary skill in art at the time of effective filing to use the teachings of Lee to include the additional substrate and contacts into the device of Fang, as doing so would increase package density within the same footprint, thus allowing for more functionality in the same size package.
Regarding Claim 15, Fang further teaches a first distance from the package contacts to the second substrate in a first direction is less than a second distance from the surface interconnect layer to the second substrate in the first direction (see Figure 12, note spacing distances on left side around 112a vs spacing in center around 122b).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kang et al. (US Patent Application Publication No. 2022/0384328)
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARK W TORNOW whose telephone number is (571)270-7534. The examiner can normally be reached M-Th 6:30-4:30 EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at 571-272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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MARK W. TORNOW
Primary Examiner
Art Unit 2891
/MARK W TORNOW/Primary Examiner, Art Unit 2891
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