DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
CONTINUED EXAMINATION UNDER 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 7/9/2026 has been entered.
RESPONSE TO ARGUMENTS
Applicant’s arguments with respect to claims 1-4, 8-14, and 18-22 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
I. REJECTIONS BASED ON PRIOR ART
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 8-14, and 18-22 are rejected under 35 U.S.C. 103 as being unpatentable over KIM et al. (US Pub.: 2022/0156002) in view of Long (US Pub.: 2022/0283974) and Verma et al. (US Pub.: 2016/0309481).
As per claim 1, KIM teaches/suggests a system for distributed data processing comprising: a plurality of tensor processing unit (TPU) clusters (e.g. associated with plurality of TPU groups in Fig. 7: [0135]), each TPU cluster having a plurality of interconnected tensor processing units (TPUs) (e.g. associated with each TPU group have plurality of TPU interconnected accordingly in Fig, 7: [0135]); inter-cluster interface, wherein the inter-cluster interface is configured to transmit data between two TPU clusters from the plurality of TPU clusters (e.g. associated with data/request being transmitted from one TPU group to another TPU group via corresponding interface: [0140]-[0142]); wherein a first interconnected TPU of a first TPU cluster is configured to direct a data transmission to a second TPU that is part of a second TPU cluster, and wherein an interface-cluster interface, from the interface-cluster interface (e.g. associated with S806 as WIO/RIO TPU of HOST TPU GROUP direct transmission to CHK TPU of CACHE TPU GROUP via corresponding bus interface in Fig. 8), and a bus interface is configured to: receive the data transmission; communicating TPU destination information for the data transmission; operating with respect to the TPU destination information; and while receiving the data transmission, provide a portion of the data transmission accordingly (e.g. associated with TPU data/request being transmitted from source TPU of one TPU group to destination TPU of another TPU group via corresponding bus interface: [0140]-[0148]) (Fig. 7-8; and [0134]-[0185]).
KIM does not teach the system for distributed data processing comprising:
a plurality of switches, wherein each switch is configured to transmit data;
wherein a first switch, from the plurality of switches, is configured to:
identify data;
access a next-hop lookup that identifies a plurality of potential output data paths by latency;
access a data-path usage table to determine whether one or more of the plurality of potential output data paths are busy;
select an available output data path, from a plurality of output data paths, based on the available output data having the lowest latency of the potential output data paths that are not identified as busy within the data-path usage table; and
provide to the available output data path.
Long teaches/suggests a system comprising: a plurality of switches, wherein each switch is configured to transmit data (e.g. associated with switching elements (211)-(212) transmitting data in Fig. 2: [0023]; [0025]-[0026]); wherein a first switch, from the plurality of switches (e.g. associated with one of the switching element (211)-(212) in Fig. 2), is configured to: identify data; select an available output data path, from a plurality of output data paths; and provide to the available output data path (e.g. associated with data being transferred/routed over the communication fabric via corresponding switching element(s): [0002]-[0003]; [0023]; [0049]) (Fig. 1-2; [0002]-[0003]; [0016]-[0040]; [0049]; and [0067]-[0071]).
Verma teaches/suggests a system comprising: access a next-hop lookup that identifies a plurality of potential output data paths by latency; access a data-path usage table to determine whether one or more of the plurality of potential output data paths are busy; select an available output data path, from a plurality of output data paths, based on the available output data having the lowest latency of the potential output data paths that are not identified as busy within the data-path usage table (e.g. equating to selecting path/channel with lowest latency that is not busy: [0050]) ([0043]; [0050]; and [0087]-[0089]).
It would have been obvious for one of ordinary skill in this art, before the effective filing date of the claimed invention, to include Long’s switching fabric and Verma’s path selection into KIM’s system for the benefit of dynamically composing groupings of computing on-the-fly (Long, [0018]) and reducing access delay (Verma, [0029]-[0030])to obtain the invention as specified in claim 1.
As per claim 2, KIM, Long and Verma teach/suggest all the claimed features of claim 1 above, where KIM, Long and Verma further teach/suggest the system comprising wherein each of the plurality of output data paths is associated with an external TPU that is part of an external TPU cluster that is different than the first TPU cluster (e.g. associated with path being associated with another group of TPU: Fig. 7-8 of KIM) (KIM, Fig. 7-8; [0134]-[0185]; Long, Fig. 1-2; [0002]-[0003]; [0016]-[0040]; [0049]; [0067]-[0071]; and Verma, [0043]; [0050]; [0087]-[0089]).
As per claim 3, KIM, Long and Verma teach/suggest all the claimed features of claim 1 above, where KIM, Long and Verma further teach/suggest the system comprising wherein the first inter-cluster switch is further configured to place received data from the data transmission into an input buffer, and wherein the TPU destination information is identified from the received data prior to receiving all of the data transmission (KIM, Fig. 7-8; [0134]-[0185]; Long, Fig. 1-2; [0002]-[0003]; [0016]-[0040]; [0049]; [0067]-[0071]; and Verma, [0043]; [0050]; [0087]-[0089), wherein it would have been obvious to one of ordinary skilled in the art to further include buffer of data as data is communicated across the switching fabric.
As per claim 4, KIM, Long and Verma teach/suggest all the claimed features of claim 1 above, where KIM, Long and Verma further teach/suggest the system comprising wherein the TPU destination information comprises a first set of bits identifying the second TPU cluster and a second set of bits identifying the second TPU (KIM, Fig. 7-8; [0134]-[0185]; Long, Fig. 1-2; [0002]-[0003]; [0016]-[0040]; [0049]; [0067]-[0071]; and Verma, [0043]; [0050]; [0087]-[0089), wherein it would have been obvious to one of ordinary skilled in the art to further implement the above claimed features.
As per claim 8, KIM, Long and Verma teach/suggest all the claimed features of claim 1 above, where KIM, Long and Verma further teach/suggest the system comprising wherein the first inter-cluster switch is further configured to have a non-blocking internal connectivity for the plurality of output data paths with respect to a plurality of input data paths (KIM, Fig. 7-8; [0134]-[0185]; Long, Fig. 1-2; [0002]-[0003]; [0016]-[0040]; [0049]; [0067]-[0071]; and Verma, [0043]; [0050]; [0087]-[0089), wherein it would have been obvious to one of ordinary skilled in the art to further implement the above claimed features.
As per claim 9, KIM, Long and Verma teach/suggest all the claimed features of claim 1 above, where KIM, Long and Verma further teach/suggest the system comprising wherein the output path corresponds to an intermediate TPU within an intermediate TPU cluster, and wherein the data transmission is provided by the intermediate TPU cluster to a second inter-cluster switch (KIM, Fig. 7-8; [0134]-[0185]; Long, Fig. 1-2; [0002]-[0003]; [0016]-[0040]; [0049]; [0067]-[0071]; and Verma, [0043]; [0050]; [0087]-[0089), wherein it would have been obvious to one of ordinary skilled in the art to further implement the above claimed features.
As per claim 10, KIM, Long and Verma teach/suggest all the claimed features of claim 9 above, where KIM, Long and Verma further teach/suggest the system comprising wherein the second inter-cluster switch is configured to: receive the data transmission; identify the TPU destination information for the data transmission; select a second output data path, from a plurality of output data paths within the second inter-cluster switch, based on the TPU destination information; and while receiving the data transmission, provide a portion of the data transmission to the second output data path (KIM, Fig. 7-8; [0134]-[0185]; Long, Fig. 1-2; [0002]-[0003]; [0016]-[0040]; [0049]; [0067]-[0071]; and Verma, [0043]; [0050]; [0087]-[0089), wherein it would have been obvious to one of ordinary skilled in the art to further implement the above claimed features.
As per claim 11, claim 11 is rejected in accordance to the same rational and reasoning as the above rejection of claim 1.
As per claim 12, KIM, Long and Verma teach/suggest all the claimed features of claim 11 above, where KIM, Long and Verma further teach/suggest the method comprising wherein the available output data path is one of a plurality of output data paths, and wherein each output data path is associated with an external TPU that is part of an external TPU cluster that is different than the first TPU cluster (e.g. associated with path being associated with another group of TPU: Fig. 7-8 of KIM) (KIM, Fig. 7-8; [0134]-[0185]; Long, Fig. 1-2; [0002]-[0003]; [0016]-[0040]; [0049]; [0067]-[0071]; and Verma, [0043]; [0050]; [0087]-[0089).
As per claim 13, KIM, Long and Verma teach/suggest all the claimed features of claim 11 above, where KIM, Long and Verma further teach/suggest the method further comprising placing, by the inter-cluster switch, received data from the data transmission into an input buffer, and wherein the TPU destination information is identified from the received data prior to receiving all of the data transmission (KIM, Fig. 7-8; [0134]-[0185]; Long, Fig. 1-2; [0002]-[0003]; [0016]-[0040]; [0049]; [0067]-[0071]; and Verma, [0043]; [0050]; [0087]-[0089), wherein it would have been obvious to one of ordinary skilled in the art to further include buffer of data as data is communicated across the switching fabric.
As per claim 14, KIM, Long and Verma teach/suggest all the claimed features of claim 11 above, where KIM, Long and Verma further teach/suggest the method comprising wherein the TPU destination information comprises a first set of bits identifying the second TPU cluster and a second set of bits identifying the second TPU within the second TPU cluster (KIM, Fig. 7-8; [0134]-[0185]; Long, Fig. 1-2; [0002]-[0003]; [0016]-[0040]; [0049]; [0067]-[0071]; and Verma, [0043]; [0050]; [0087]-[0089), wherein it would have been obvious to one of ordinary skilled in the art to further implement the above claimed features.
As per claim 18, KIM, Long and Verma teach/suggest all the claimed features of claim 11 above, where KIM, Long and Verma further teach/suggest the method further comprising providing, by the inter-cluster switch, the data transmission to the available data path over a plurality of non-blocking sub-switches (KIM, Fig. 7-8; [0134]-[0185]; Long, Fig. 1-2; [0002]-[0003]; [0016]-[0040]; [0049]; [0067]-[0071]; and Verma, [0043]; [0050]; [0087]-[0089), wherein it would have been obvious to one of ordinary skilled in the art to further implement the above claimed features.
As per claim 19, KIM, Long and Verma teach/suggest all the claimed features of claim 11 above, where KIM, Long and Verma further teach/suggest the method comprising wherein the output path corresponds to an intermediate TPU within an intermediate TPU cluster and the inter-cluster switch is a first inter-cluster switch, further comprising providing the data transmission, by the intermediate TPU cluster, to a second inter-cluster switch (KIM, Fig. 7-8; [0134]-[0185]; Long, Fig. 1-2; [0002]-[0003]; [0016]-[0040]; [0049]; [0067]-[0071]; and Verma, [0043]; [0050]; [0087]-[0089), wherein it would have been obvious to one of ordinary skilled in the art to further implement the above claimed features.
As per claim 20, KIM, Long and Verma teach/suggest all the claimed features of claim 19 above, where KIM, Long and Verma further teach/suggest the method further comprising: receiving the data transmission at the second inter-cluster switch; identifying, by the second inter-cluster switch, the TPU destination information for the data transmission; selecting, by the second inter-cluster switch, a second output data path, from a plurality of output data paths within the second inter-cluster switch, based on the TPU destination information; and while receiving the data transmission, providing, by the second inter-cluster switch, a portion of the data transmission to the second output data path (KIM, Fig. 7-8; [0134]-[0185]; Long, Fig. 1-2; [0002]-[0003]; [0016]-[0040]; [0049]; [0067]-[0071]; and Verma, [0043]; [0050]; [0087]-[0089), wherein it would have been obvious to one of ordinary skilled in the art to further implement the above claimed features.
As per claim 21, KIM, Long and Verma teach/suggest all the claimed features of claim 1 above, where KIM, Long and Verma further teach/suggest the system comprising: wherein, in the event that all potential output data paths identified by the next-hop lookup for the TPU destination information are determined to be currently busy in the data-path usage table, the first inter-cluster switch is configured to select an idle port from the data-path usage table and provide the data transmission via the selected idle port (KIM, Fig. 7-8; [0134]-[0185]; Long, Fig. 1-2; [0002]-[0003]; [0016]-[0040]; [0049]; [0067]-[0071]; and Verma, [0043]; [0050]; [0087]-[0089), wherein it would have been obvious to one of ordinary skilled in the art to further implement the above claimed features.
As per claim 22, KIM, Long and Verma teach/suggest all the claimed features of claim 11 above, where KIM, Long and Verma further teach/suggest the method comprising: wherein, in the event that all potential output data paths identified by the next-hop lookup for the TPU destination information are determined to be currently busy in the data-path usage table, the method further comprises selecting, by the inter-cluster switch, an idle port from the data-path usage table and providing the data transmission via the selected idle port (KIM, Fig. 7-8; [0134]-[0185]; Long, Fig. 1-2; [0002]-[0003]; [0016]-[0040]; [0049]; [0067]-[0071]; and Verma, [0043]; [0050]; [0087]-[0089), wherein it would have been obvious to one of ordinary skilled in the art to further implement the above claimed features.
III. CLOSING COMMENTS
CONCLUSION
STATUS OF CLAIMS IN THE APPLICATION
The following is a summary of the treatment and status of all claims in the application as recommended by M.P.E.P. 707.07(i):
CLAIMS REJECTED IN THE APPLICATION
Per the instant office action, claims 1-4, 8-14, and 18-22 have received a first action on the merits and are subject of a first action non-final.
DIRECTION OF FUTURE CORRESPONDENCES
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHUN KUAN LEE whose telephone number is (571)272-0671. The examiner can normally be reached Monday-Friday.
IMPORTANT NOTE
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Idriss Alrobaye can be reached on (571) 270-1023. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/CHUN KUAN LEE/Primary Examiner
Art Unit 2181 August 27, 2026
Prosecution Insights