DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restrictions
Applicant’s election of species A, fig. 1, claims 1-20, in the reply filed on 6/18/26 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Allowable Subject Matter
Claims 4-9, 15-17 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 3, 10-13, 18 and 19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kanno, US Publication No. 2021/0066340 A1.
Kanno anticipates:
1. A semiconductor device comprising (see figs. 5, 6, 8 and 19):
a first substrate (30);
a wire portion (D0/C2/D1) on the first substrate;
a second substrate (41) on the wire portion;
a first gate stacking structure (e.g. lower 45) on the second substrate;
a second gate stacking structure (e.g. upper 45) on the first gate stacking structure; and
a channel structure (MP) passing through the first gate stacking structure and the second gate stacking structure and connected to the second substrate,
wherein the second substrate (41B/41A in fig. 8; 41D/41A in fig. 19) includes a first material layer (41B; 41D) and a second material layer on the first material layer,
the first material layer (41B; 41D) includes polysilicon including a first material,
the second material layer (41A) includes polysilicon including a second material different from the first material, and
an insulation layer (E1) is disposed between the wire layer and the second substrate. See Kanno at para. [0001] – [0144], figs. 1-21.
3. The semiconductor device of claim 1, wherein the first material layer (41Dc) includes polysilicon doped with carbon, and the second material layer (41A) includes n-doped polysilicon, para. [0082], [0109], fig. 19.
10. The semiconductor device of claim 1, wherein
the channel structure (MP) includes
a channel layer (61), and
a gate dielectric layer (62) disposed between the channel layer and the first and second gate stacking structures (45), fig. 5.
11. The semiconductor device of claim 10, further comprising
a horizontal conductive layer (41C) disposed on the second substrate,
wherein the horizontal conductive layer electrically connects the second substrate (41B/41A in fig. 8; 41D/41A in fig. 19) and the channel layer (41C), figs. 5, 8 and 19.
12. The semiconductor device of claim 11, wherein
the channel structure (MP) further includes a core insulation layer (60) surrounded by the channel layer (61), and
the gate dielectric layer (62) includes a tunneling layer (63), a charge storage layer (64), and a blocking layer (65) sequentially stacked on the channel layer, fig. 6.
Regarding claim 13:
Kanno teaches the limitations as applied to claims 1 and 3 above.
Kanno further teaches the added limitations:
where the wire portion (D0/C2/D1) includes a wire layer (D0, D1) and an insulation layer (E1) covering the wire layer, fig. 5.
Regarding claim 18:
Kanno teaches the limitations as applied to claim above.
Kanno further teaches the added limitations:
a controller (2 in fig. 1) electrically connected to the semiconductor device on the main substrate,
(see fig. 5) wherein the semiconductor device includes a circuit region (PE) and a cell region (40) disposed in the circuit region.
Regarding claim 19:
Kanno teaches the limitations as applied to claim 3 above.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kanno, as applied to claims 1 and 13 above.
Regarding claim 2:
Kanno teaches all the limitations of claim 1 above but does not expressly teach:
wherein the first material layer and the second material layer have different values of etching selectivity.
However, it would have been obvious to one of ordinary skill in the art to form “the first material layer (e.g. 41Dc) and the second material layer (41A) have different values of etching selectivity” because they comprise different materials at para. [0082], [0109], fig. 19.
Furthermore, Kanno teaches materials for the first material layer and the second material layer that is substantially identical to Applicant’s materials. Therefore, the property of “different values of etching selective” is necessarily present. See MPEP 2112:
“Products of identical chemical composition can not have mutually exclusive properties.” A chemical composition and its properties are inseparable. Therefore, if the prior art teaches the identical chemical structure, the properties applicant discloses and/or claims are necessarily present. In re Spada, 911 F.2d 705, 709, 15 USPQ2d 1655, 1658 (Fed. Cir. 1990)
Regarding claim 14:
Kanno teaches the limitations as applied to claim 2 above.
Relevant Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Shioda, US 20190067317 A1 (Shioda teaches in fig. 18 a second substrate comprising a first material layer (12) and second material layer (84).)
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Michele Fan whose telephone number is 571-270-7401. The examiner can normally be reached on M-F from 7:30 am to 4 pm.
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/Michele Fan/
Primary Examiner, Art Unit 2818
28 August 2026
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