Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized claim limitations indicate limitations that are not explicitly disclosed in the primary reference, but disclosed in the secondary reference(s).
Claims 1-4, 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 11373933 B2) in view of Yeh (US 20210183813 A1).
Regarding claim 1, Lee discloses a semiconductor package (Fig. 6B), comprising:
a first substrate (110);
a first semiconductor device (120) on the first substrate, the first semiconductor device including a first surface (See annotated figure) and an opposing second surface (See annotated figure), with a chip pad (121) on the first surface;
a mold layer (MD2) covering (covering in the D3/vertical direction, See annotated figure for direction designation) the first substrate and the second surface of the first semiconductor device;
a conductive pillar (CT1) that penetrates the mold layer (fully vertically penetrates); and
a second substrate (180) placed on a top surface (See annotated figure for “top” direction designation) of the mold layer (directly on) and the conductive pillar (directly on),
the second substrate being closer to the second surface of the first semiconductor device than it is to the first surface of the first semiconductor device (closer in the D3 direction),
wherein: the mold layer includes grooves (See annotated figure) that are closer to the second surface of the first semiconductor device than they are to the first surface of the first semiconductor device (closer in the D3 direction);
the grooves of the mold layer are spaced apart from the second surface of the first semiconductor device (spaced apart in the D3 direction);
a level of the second surface of the first semiconductor device is lower than a level of a top surface of the conductive pillar (lower in the D3 direction, See annotated figure for “lower” direction designation),
wherein the second surface of the first semiconductor device is the uppermost surface of the first semiconductor device (See annotated figure for “upper” direction designation), and
the second substrate comprises:
a first opening (the collection of TH defined as THP) that exposes (directly exposes) the grooves of the mold layer,
the first opening comprising a first width (W1), at a top of the first opening adjacent to a top of the second substrate (coplanar, thus adjacent), that is larger than a second width (W1b, See annotated figure) at a bottom of the first opening adjacent to the mold layer (See annotated figure for “bottom” designation),
wherein the top surface of the mold layer comprises a planar surface portion (See dashed reference line showing the designated plane of MD2) extending from the conductive pillar (this plane directly contacts the pillar), at a first surface end of the planar surface portion, to the grooves (this plane directly contacts the grooves), at an opposing second surface end of the planar surface portion,
the planar surface portion, the first surface end, and the second surface end lying within the same plane (a single continuous plane is shown) that is parallel to the second surface of the first semiconductor device (parallel in the D1 and D2 directions);
a first redistribution dielectric layer (of 180; col. 4, lines. 47-57: “a dielectric substrate”; the layer surrounding 182) and a second redistribution dielectric layer (of 180; col. 4, lines. 47-57: “a dielectric substrate”; the layer surrounding 184) that are sequentially stacked (stacked in the D3 direction. Note: Lee is relied upon here to teach a generic dielectric layer and redistribution pattern configuration. Additional remarks and citations are provided below with Yeh regarding the first and second layers and their stacked configuration.) with inclined sidewalls (inclined sidewalls are shown) being offset from each other to form a stepwise structure, wherein the sidewalls face the first opening (directly face), and a first redistribution pattern between the first redistribution dielectric layer and the second redistribution dielectric layer.
Illustrated below is a marked and annotated figure of Fig. 6B of Lee.
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Lee teaches the second substrate, but fails to teach specific structural configurations of it. Thus, Lee fails to teach “a first redistribution dielectric layer and a second redistribution dielectric layer that are sequentially stacked with inclined sidewalls being offset from each other to form a stepwise structure, wherein the sidewalls face the first opening, and a first redistribution pattern between the first redistribution dielectric layer and the second redistribution dielectric layer.”
Yeh discloses the second substrate comprises: a first redistribution dielectric layer (152a) and a second redistribution dielectric layer (152b) that are sequentially stacked (stacked in the Z direction) with inclined sidewalls (the inclined sidewalls being R2s; [0049] “substantially slant lines and substantially horizontal lines interconnected”) being offset from each other (offset in the X direction) to form a stepwise structure (steps are shown), wherein the sidewalls face the first opening (directly face opening R2), and a first redistribution pattern (156a) between (between in the Z direction) the first redistribution dielectric layer and the second redistribution dielectric layer.
Modifying the second substrate of Lee by including dielectric layers and a redistribution pattern in the way disclosed by Yeh would arrive at the claimed dielectric layer configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because in each situation the second substrate is performing the same function to redistribute from underlying components (Lee: Fig. 6B: the patterns of 182 function to redistribute from conductive patterns CT1 of underlying components; Yeh: Fig. 4: the underlying components being at least 130d). Yeh teaches a motivation for one of ordinary skill in the art before the effective filing date to modify the dielectric layers in that it may be varied as a design choice according to required circuitry design ([0037]: “based on the demand and/or design layout”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed dielectric layer configuration because it is a design choice chosen according to design requirements. MPEP 2143 (I)(G).
Illustrated below is a marked and annotated figure of Fig. 4 of Yeh.
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Regarding claim 2, Lee in view of Yeh discloses the semiconductor package as claimed in claim 1 (Yeh: Fig. 4), wherein an offset distance between the sidewalls of the first and second redistribution dielectric layers (a zero offset in the Z direction) is smaller than a first thickness of the first redistribution dielectric layer (a thickness greater than zero is illustrated) and smaller than a second thickness of the second redistribution dielectric layer (a thickness greater than zero is illustrated).
Regarding claim 3, Lee in view of Yeh discloses the semiconductor package as claimed in claim 2 (Yeh: Fig. 4), wherein the first thickness (the Z-direction thickness of 152a includes a thickness of a via portion of 156a without a thickness of a wiring portion) is less than the second thickness (the Z-direction thickness of 152b includes a thickness of a via portion of 156b in combination with a thickness of a wiring portion of 156a, therefore the second thickness is greater by at least the thickness of the wiring portion of 156a).
Regarding claim 4, Lee in view of Yeh discloses the semiconductor package as claimed in claim 1 (Yeh: Fig. 4), wherein an exposed top surface of the first redistribution dielectric layer (See annotated figure) has a width (See annotated figure) of about 1 μm to about 7 μm, the width of the exposed top surface of the first redistribution dielectric layer being equal (exactly equal) to an offset distance between the sidewalls of the first and second redistribution dielectric layers and being exposed without being covered with the second redistribution dielectric layer (exposed/not covered in the Z direction).
Lee in view of Yeh discloses the claimed invention, but is silent regarding the range endpoints for the width of the exposed top surface of the first redistribution dielectric layer. Thus, the combination of references fails to teach “a width of about 1 µm to about 7 µm”. However, the width is disclosed by Yeh as being variable to include zero width as well as widths greater than zero (Yeh: [0049]: “a substantially slant line” and “offset”), thus the specific width chosen does not appear critical. Additionally, Yeh discloses dimensional ranges for other features related to the first redistribution dielectric layer, thereby establishing a scale on the order of ones of µm ([0050]: “The distance D”); and this scale is reasonably close to the claimed width range (i.e., “about 1 µm to about 7 µm”). Therefore, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date to have an exposed top surface with the claimed range, because a prima facie case of obviousness exists where the claimed ranges or amounts do not overlap with the prior art but are merely close. Titanium Metals Corp. of America v. Banner, 778 F.2d 775, 783, 227 USPQ 773, 779 (Fed. Cir. 1985). MPEP 2144.05 (I).
Regarding claim 6, Lee in view of Yeh discloses the semiconductor package as claimed in claim 1 (Lee: Fig. 6B), further comprising: an upper semiconductor package (200) on the second substrate; and an under-fill layer (MD1. Note: this layer is under package 200 and filling opening THP, thus it is an underfill) between the upper semiconductor package and the second substrate (between in the D3 direction), the under-fill layer filling the first opening (completely filling).
Regarding claim 7, Lee in view of Yeh discloses the semiconductor package as claimed in claim 6 (Lee: Fig. 6B), wherein the under-fill layer fills the grooves (completely fills).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Yeh as applied to claim 1 above, and further in view of Lin (US 20170084543 A1).
Regarding claim 5, Lee in view of Yeh discloses the semiconductor package as claimed in claim 1 (Lee: Fig. 6B), wherein the grooves have a depth of about 15 μm to about 20 μm from the top surface of the mold layer, and a thickness of the mold layer on the first semiconductor device is about 30 μm to about 40 μm.
Lee in view of Yeh discloses the claimed invention, but is silent regarding the range endpoints for the depth of the grooves. Thus, the combination of references fails to teach “a depth of about 15 μm to about 20 μm”.
However, groove depth range endpoints are known in the art. Lin discloses the grooves have a depth (Lin: Fig. 8A: D1) of about 15 μm to about 20 μm from the top surface of the mold layer ([0078]: “a depth of 15.8 μm” being one of a plurality of embodiments and falling squarely within the claimed range). Modifying the groove depth of Lee in view of Yeh, by incorporating the range endpoints of Lin would arrive at the claimed groove configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because in each situation, a groove is formed in a mold layer (Lee: Fig. 6B: mold MD2 and the annotated grooves; Lin: Fig. 8A: mold 105 and groove 805). Therefore, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date to have the claimed groove depth because the prior art teaches an overlapping range used in a similar situation. MPEP 2144.05 (I).
Lee in view of Yeh discloses the claimed invention, but is silent regarding the range endpoints for the thickness of the mold layer. Thus, the combination of references fails to teach “about 30 μm to about 40 μm”.
However, mold layer thickness range endpoints are known in the art. Lin discloses mold layer thickness may be variable ([0024]: “any suitable method and thickness”) and discloses thickness being greater than the groove depth ([0070]: “depth D1 that is less than the first thickness T1”). As reasoned above, Lin discloses the groove depth may include 15-20 μm, thus the mold layer thickness must be greater than 15-20 μm. This thickness reasonably establish a scale on the order of tens of μm; and this scale is reasonably close to the claimed thickness range (i.e., “about 30 µm to about 40 µm”). Therefore, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date to have a thickness of the mold layer on the first semiconductor device with the claimed range, because a prima facie case of obviousness exists where the claimed ranges or amounts do not overlap with the prior art but are merely close. Titanium Metals Corp. of America v. Banner, 778 F.2d 775, 783, 227 USPQ 773, 779 (Fed. Cir. 1985). MPEP 2144.05 (I).
Illustrated below is a marked and annotated figure of Fig. 8A of Lin.
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Claims 8-13, 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Yeh and Lin.
Regarding independent claim 8, Lee discloses a semiconductor package (Fig. 10D), comprising:
a first substrate (110);
a first semiconductor device (120) on the first substrate, the first semiconductor device including a first surface (See annotated figure) and an opposing second surface (See annotated figure), and a chip pad (121) on the first surface;
a mold layer (MD2) covering (covering in the D3/vertical direction, See annotated figure for direction designation) the first substrate and the second surface of the first semiconductor device;
a second substrate (180) on the mold layer (directly on),
the second substrate being closer to the second surface of the first semiconductor device than it is to the first surface of the first semiconductor device (closer in the D3 direction);
an upper semiconductor package (Fig. 6B: package 200. Note: this package is applied in the same way to the same connections 184 of the selected Fig. 10D embodiment. The selected embodiment is merely illustrated as an intermediately formed device, while Fig. 6B is a completed device.) on the second substrate; and
an under-fill layer (MD1. Note: this layer is under package 200 and filling an opening, thus it is an underfill) between the upper semiconductor package and the mold layer (between in the D3 direction, See annotated figure for direction designation),
wherein: the second substrate comprises a plurality of dielectric layers (of 180; col. 4, lines 47-57: “a dielectric substrate”; the layer surrounding 182 and the layer surrounding 184. Note: Lee is relied upon here to teach a generic dielectric layer configuration. Additional remarks and citations are provided below with Yeh regarding the plurality of layers.) and a plurality of redistribution patterns (182. Note: the patterns of 182 function to redistribute from conductive patterns CT1 of underlying components),
the mold layer comprises a groove, the groove is closer to the second surface of the first semiconductor device than it is to the first surface of the first semiconductor device,
the plurality of dielectric layers includes an opening (See annotated figure) exposing the groove, the under-fill layer disposed in the opening (MD1 is in the designated opening) and the groove,
wherein the mold layer comprises a recess region (See annotated figure) exposed to the opening (directly exposed), and a sidewall of the recess region is inclined at an oblique angle relative to a bottom surface of the recess region (See annotated figure), and the sidewall of the recess region is coplanar with a first sidewall of a first redistribution dielectric layer (Note: at least one dielectric layer is shown. This layer is being designated as the first layer.) of the plurality of dielectric layers (See dashed reference line), and the first sidewall is inclined at the oblique angle relative to the bottom surface of the recess region (this sidewall used the same oblique angle because of the coplanarity), and
a bottommost surface of the groove is spaced apart from the second surface of the first semiconductor device.
Illustrated below is a marked and annotated figure of Fig. 10d of Lee.
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Lee teaches the second substrate, but fails to teach specific structural configurations of it. Thus, Lee fails to teach “the second substrate comprises a plurality of dielectric layers and a plurality of redistribution patterns,” and
“the plurality of dielectric layers includes an opening exposing the groove, the under-fill layer disposed in the opening and the groove,” and
“the sidewall of the recess region is coplanar with a first sidewall of a first redistribution dielectric layer of the plurality of dielectric layers, and the first sidewall is inclined at the oblique angle relative to the bottom surface of the recess region,”.
Yeh discloses the second substrate comprises
a plurality of dielectric layers (152a, 152b) and a plurality of redistribution patterns (156a), [and]
the plurality of dielectric layers includes an opening (opening R2).
Modifying the second substrate of Lee by including the plurality of dielectric layers and redistribution patterns in the way disclosed by Yeh would arrive at the claimed dielectric layer configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because in each situation the second substrate is performing the same function to redistribute from underlying components (Lee: Fig. 6B: the patterns of 182 function to redistribute from conductive patterns CT1 of underlying components; Yeh: Fig. 4: the underlying components being at least 130d). Yeh teaches a motivation for one of ordinary skill in the art before the effective filing date to modify the plurality of dielectric layers in that it may be varied as a design choice according to required circuitry design ([0037]: “based on the demand and/or design layout”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed plurality of dielectric layers configuration because it is a design choice chosen according to design requirements. MPEP 2143 (I)(G).
Leefails to teach the mold layer comprises a groove. Thus, Lee in view of Yeh fails to teach “the mold layer comprises a groove, the groove is closer to the second surface of the first semiconductor device than it is to the first surface of the first semiconductor device,
the plurality of dielectric layers includes an opening exposing the groove, the under-fill layer disposed in the opening and the groove,” and
“a bottommost surface of the groove is spaced apart from the second surface of the first semiconductor device”.
Lin discloses the mold layer (Fig. 8A: 105) comprises a groove (802), the groove is closer to the second surface of the first semiconductor device (See annotated figure, closer to device 201 in the vertical direction) than it is to the first surface of the first semiconductor device (See annotated figure), […] and a bottommost surface of the groove is spaced apart from the second surface of the first semiconductor device (spaced apart by intervening 105).
Modifying the mold layer of Lee in view of Yeh by including the groove of Lin (by including it on the exposed surface of Lee’s mold layer vertically overlapping the first semiconductor device. Lee: mold MD2 exposed by the opening, overlapping device 120), would arrive at the claimed groove configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because in each situation, an exposed mold layer overlaps a device (Lee: mold MD2 exposed by the opening, overlapping device 120; Lin: Fig. 8A: mold 105 overlapping device 201). Lin provides a teaching to motivate one of ordinary skill in the art before the effective filing date to include the groove on the mold layer in that it would enable the inclusion of additional information within the manufacturing process, thereby enhancing manufacturing capability ([0063]: “identifying or information mark”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed groove because it would enhance manufacturing capability. MPEP 2143 (I)(G).
Regarding claim 9, Lee in view of Yeh and Lin discloses the semiconductor package as claimed in claim 8 (Lee: Fig. 10D), wherein a width of the opening (W1, See annotated figure) is greater than a width of the groove (“greater” because oblique angle of the sidewalls produces a smaller surface for the grooves).
Regarding claim 10, Lee in view of Yeh and Lin discloses the semiconductor package as claimed in claim 8 (Lin: Fig. 8A), wherein the groove is one of a plurality of grooves in the mold layer (multiple 802 are shown for each device), each groove closer to the second surface of the first semiconductor device than it is to the first surface of the first semiconductor device (See annotated figure), and a bottommost surface of each groove spaced apart from the second surface of the first semiconductor device (spaced apart by intervening 105).
Regarding claim 11, Lee in view of Yeh and Lin discloses the semiconductor package as claimed in claim 10 (Lee: Fig. 10D), wherein a width of the opening (W1, See annotated figure) is greater than the sum of widths of the plurality of grooves (“greater” because oblique angle of the sidewalls produces a smaller surface for the grooves).
Regarding claim 12, Lee in view of Yeh and Lin discloses the semiconductor package as claimed in claim 8 (Lee: Fig. 10D), further comprising an internal connection member (124) between the chip pad and the first substrate.
Regarding claim 13, Lee in view of Yeh and Lin discloses the semiconductor package as claimed in claim 8 (Lee: Fig. 10D), further comprising a conductive pillar (CT1) that penetrates the mold layer (fully penetrates), wherein a top surface of the conductive pillar (a curved surface facing upwards, See annotated figure) is lower than a top surface of the mold layer (See annotated figure for surface designation).
Regarding claim 15, Lee in view of Yeh and Lin discloses the semiconductor package as claimed in claim 8 (Lin: Fig. 8A), wherein the groove has a depth (D1) from the bottom surface of the recess region.
Regarding claim 16, Lee in view of Yeh and Lin discloses the semiconductor package as claimed in claim 15 (Lee: Fig. 10D), wherein the sidewall of the recess region is inclined at an angle that is greater than 90 degrees (the oblique angle is shown substantially greater than 90 degrees) relative to the bottom surface of the recess region.
Claims 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 20190067258 A1) in view of Yeh and Lin.
Regarding independent claim 18, Kim discloses a semiconductor package (Fig. 2), comprising:
a first substrate (110);
a first semiconductor device (120) on the first substrate, the first semiconductor device including a first surface (See annotated figure) and an opposing second surface (See annotated figure) with a chip pad (See annotated figure) on the first surface;
a mold layer (200) covering the first substrate (covering in the D3 direction) and the second surface of the first semiconductor device (covering in the D3 direction); and
a second substrate (300) on a top surface of the mold layer (See annotated figure for “top” direction designation. Note: a dashed reference line has been added tracing a portion of the “top surface of the mold layer”), the second substrate being closer to the second surface of the first semiconductor device than it is to the first surface of the first semiconductor device (closer in the D3 direction),
wherein: the second substrate comprises a plurality of dielectric layers and a plurality of redistribution patterns ([0026]: “The redistributed conductive patterns”. Note: the patterns of 300 function to redistribute from conductive patterns 330 of underlying components),
the mold layer comprises a first groove and a second groove,
the plurality of dielectric layers includes a first opening (305) exposing the first groove and a second opening exposing the second groove,
the first opening comprising a first width (305 as measured in the D1 direction), at a top of the first opening adjacent to a top of the second substrate (See annotated figure for “top” direction designation), that is larger than a second width (305 as measured in the D1 direction) at a bottom of the first opening adjacent to the mold layer (See annotated figure for “bottom” direction designation),
wherein the top surface of the mold layer comprises a planar surface portion (See annotated figure pointing to the designated “planar surface portion”) extending from below the second substrate (below in the D3 direction), at a first surface end of the planar surface portion (See annotated figure), to the first groove, at an opposing second surface end of the planar surface portion (See annotated figure),
the planar surface portion, the first surface end, and the second surface end lying within the same plane (a D1/out-of-page plane) that is parallel (parallel in the D1 direction) to the second surface of the first semiconductor device, and
a level of a bottommost surface of the first groove and a level of a bottommost surface of the second groove are each higher than a level of the second surface of the first semiconductor device,
wherein the second surface of the first semiconductor device is the uppermost surface of the first semiconductor device (this is the spatial designation chosen for interpreting the reference, See annotated figure).
Illustrated below is a marked and annotated figure of Fig. 2 of Kim.
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Kim fails to teach detailed construction of the second substrate, and thus fails to teach “wherein: the second substrate comprises a plurality of dielectric layers and a plurality of redistribution patterns” and
“the plurality of dielectric layers includes a first opening exposing the first groove and a second opening exposing the second groove,
the first opening comprising a first width, at a top of the first opening adjacent to a top of the second substrate, that is larger than a second width at a bottom of the first opening adjacent to the mold layer,”
Yeh discloses a similar second substrate (Fig. 4: 150)
wherein: the second substrate comprises a plurality of dielectric layers (at least 152a and 152b) and a plurality of redistribution patterns (at least 156a and 156b), and
the mold layer comprises a first groove and a second groove,
the plurality of dielectric layers includes a first opening (R2) exposing the first groove and a second opening exposing the second groove,
the first opening comprising a first width (Wt), at a top of the first opening adjacent to a top of the second substrate, that is larger than a second width (Wb) at a bottom of the first opening adjacent to the mold layer (140, adjacent in the Z direction),
Modifying the second substrate of Kim by including a plurality of dielectric layers and redistribution patterns in the way disclosed by Yeh would arrive at the claimed first opening and second substrate configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because in each situation the second substrate is performing the same function to redistribute from underlying components (Kim: Fig. 2: the patterns of 300 function to redistribute from conductive patterns 330 of underlying components; Yeh: Fig. 4: the underlying components being at least 130d). Yeh teaches a motivation for one of ordinary skill in the art before the effective filing date to modify the second substrate and the first opening in that it may be varied as a design choice according to required circuitry design ([0037]: “based on the demand and/or design layout”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed second substrate and first opening configuration because it is a design choice chosen according to design requirements. MPEP 2143 (I)(G).
Kim in view of Yeh fails to teach “the plurality of dielectric layers includes a first opening exposing the first groove and a second opening exposing the second groove,”.
However, Yeh discloses the number and function of first semiconductor devices may be varied as a design choice to be more than one ([0027]: “additional semiconductor die(s) of the same type or different types”). Modifying the number of first semiconductor devices of Kim by pluralizing the configuration cited above would arrive at the claimed first and second openings. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because Yeh discloses the number and function of first semiconductor devices may be varied as a design choice to be more than one ([0027]: “additional semiconductor die(s) of the same type or different types”). Yeh provides a teaching to motivate one to modify the number of first semiconductor devices and the configurations therefor, in that it is a design choice that would enable a package having alternative utility ([0027]: “the same type or different types” in combination with the alternative functions listed). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the first and second opening because it would enable a package having alternative utility. MPEP 2143 (I)(G).
Kim in view of Yeh fails to teach “the mold layer comprises a first groove and a second groove,
the plurality of dielectric layers includes a first opening exposing the first groove and a second opening exposing the second groove,
the first opening comprising a first width, at a top of the first opening adjacent to a top of the second substrate, that is larger than a second width at a bottom of the first opening adjacent to the mold layer,
wherein the top surface of the mold layer comprises a planar surface portion extending from below the second substrate, at a first surface end of the planar surface portion, to the first groove, at an opposing second surface end of the planar surface portion,” and
“a level of a bottommost surface of the first groove and a level of a bottommost surface of the second groove are each higher than a level of the second surface of the first semiconductor device,”
Lin discloses the mold layer (Fig. 8A: 105) comprises a first groove (802) and a second groove, […] and
a level of a bottommost surface of the first groove and a level of a bottommost surface of the second groove are each higher than a level of the second surface of the first semiconductor device (higher in the vertical direction).
Modifying the mold layer of Kim in view of Yeh by including the groove of Lin, i.e., on the exposed surface of Kim’s mold layer overlapping the pluralized first semiconductor device, would arrive at the claimed first and second groove configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because in each situation the mold layer includes an exposed surface overlapping a first semiconductor device (Lin: See annotated figure for exposed surface, overlapping device 201; Kim: See annotated figure for exposed surface, overlapping device 120). Lin provides a teaching to motivate one of ordinary skill in the art before the effective filing date to include the grooves on the mold layer in that it would enable the inclusion of additional information within the manufacturing process, thereby enhancing manufacturing capability ([0063]: “identifying or information mark”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed grooves because it would enhance manufacturing capability. MPEP 2143 (I)(G).
Regarding claim 19, Kim in view of Yeh and Lin discloses the semiconductor package as claimed in claim 18 (Lin: Fig. 8A), wherein the first groove is one of a plurality of first grooves (two 802 are illustrated for a corresponding 201) and the second groove is one of a plurality of second grooves (the two 802 illustrated reasonably apply to the pluralized first semiconductor devices), the first opening exposes the plurality of first grooves, the second opening exposes the plurality of second grooves (the pluralities of grooves being on the exposed surface of the mold layer, in the same way as before in the claim 18 rejection), and a level of a bottommost surface of each groove of the plurality of first grooves and a level of a bottommost surface of each groove of the plurality of second grooves are each higher than the level of the second surface of the first semiconductor device (higher in the vertical direction).
Regarding claim 20, Kim in view of Yeh and Lin discloses the semiconductor package as claimed in claim 18 (Yeh: Fig. 4), wherein the second opening comprises a third width (Wt, reasonably applied to the second opening in the same way as applied to the first opening), at a top of the second opening adjacent to the top of the second substrate, that is larger than a fourth width at a bottom of the second opening adjacent to the mold layer (Wb, adjacent to 140, reasonably applied to the second opening in the same way as applied to the first opening).
Claims 14 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Yeh and Lin as applied to claim 8 above, and further in view of Cheng (US 9159678 B2).
Regarding claim 14, Lee in view of Yeh and Lin discloses the semiconductor package as claimed in claim 8 (Lee: Fig. 10D), further comprising a conductive pillar (CT1) that penetrates the mold layer (fully penetrates), wherein the redistribution patterns penetrate the mold layer to connect with the conductive pillar (direct electrical connection).
Lee in view of Yeh and Lin fails to teach the redistribution patterns “penetrate the mold layer to connect with the conductive pillar” when interfacing with the mold layer.
Cheng discloses a conductive pillar (Fig. 1: 106) that penetrates the mold layer (penetrates mold layer 107), wherein the redistribution patterns (113) penetrate the mold layer to connect with the conductive pillar (113 penetrates 107 to connect with 106). Modifying the redistribution patterns, mold layer, and conductive pillar configuration of Lee in view of Yeh and Lin by incorporating the structural configuration disclosed by Cheng would arrive at the claimed structural configuration of the redistribution structures. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because in each situation the redistribution patterns are connecting with conductive pillars that penetrate a mold layer. Cheng provides a teaching to motivate one to modify the configuration of Lee in that it would protect the device from damage, thereby enhancing device reliability (col. 4, lines 29-38: “prevent a development of cracks… improve a reliability”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed conductive pillar, mold layer, and redistribution patterns configuration because it would enhance device reliability. MPEP 2143 (I)(G).
Regarding claim 17, Lee in view of Yeh and Lin discloses the semiconductor package as claimed in claim 8 (Lee: Fig. 10D), further comprising
a connection substrate (CT1. Note: this structure is a physical body upon which subsequent features are formed or placed upon, thus it is a substrate) on the first substrate,
the connection substrate including a cavity region (the region occupied by 120 has no CT1, thus it is a region with a cavity) into which the first semiconductor device is inserted,
wherein the mold layer fills a space between the first semiconductor device and the connection substrate (MD2 completely separates 120 and CT1), and between the second substrate and the connection substrate (at least some MD2 is between the barrel shaped CT1 and 180 in the D3 direction), and
wherein a portion of a first redistribution pattern penetrates a first redistribution dielectric layer of the plurality of dielectric layers (as previously cited, 182 is surrounded by the first dielectric layer, thus it “penetrates”) and the mold layer to electrically connect with the connection substrate (direct electrical connection).
Lee in view of Yeh and Lin fails to teach the first redistribution pattern “penetrates a first redistribution dielectric layer of the plurality of dielectric layers and the mold layer to electrically connect with the connection substrate” when interfacing with the mold layer.
Cheng discloses a portion of a first redistribution pattern (Fig. 1: 113) penetrates a first redistribution dielectric layer (109) of the plurality of dielectric layers and the mold layer (107) to electrically connect with the connection substrate (113 penetrates 107 to connect with 106). Modifying the redistribution patterns, mold layer, and conductive pillar configuration of Lee in view of Yeh and Lin by incorporating the structural configuration disclosed by Cheng would arrive at the claimed structural configuration of the redistribution pattern. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because in each situation the redistribution patterns are connecting with conductive pillars that penetrate a mold layer. Cheng provides a teaching to motivate one to modify the configuration of Lee in that it would protect the device from damage, thereby enhancing device reliability (col. 4, lines 29-38: “prevent a development of cracks… improve a reliability”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed conductive pillar, mold layer, and redistribution patterns configuration because it would enhance device reliability. MPEP 2143 (I)(G).
Response to Arguments
Applicant's arguments filed 2/18/2026 have been fully considered but they are not persuasive.
Applicant argues:
Applicant argues with respect to amended claims 1 and 18 that “the proposed combination of Kim, Yeh, and Lin fails to teach the features of claims 1 and 18”. Remarks at pg. 7.
Examiner’s reply:
Applicant’s arguments with respect to claim(s) 1 and 18 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant argues:
Applicant argues with respect to amended claim 8 that “the proposed combination of Kim, Yeh, Lin, and Chen fails to teach the features of claim 8”. Remarks at pg. 10.
Examiner’s reply:
Applicant’s arguments with respect to claim(s) 8 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/WILLIAM H ANDERSON/ Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817 March 27, 2026