DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 2, and 5-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yang (US 20220310824 A1).
Regarding claim 1, Yang teaches a structure (HEMT, [0015], Fig 13) comprising:
a gate structure (GS: layers 208/222) on (shown on) a semiconductor substrate (Sub: layers 202/203/204/206);
a gate metal (232) connecting (shown connected) to the gate structure (GS) and offset (shown offset) from edges (222SW: sidewall edges of 222) of the gate structure (GS); and
inner sidewall spacers (224) on (shown on) an upper surface (222T: top surface of 222) of the gate structure (GS) and surrounding (shown surrounding) the gate metal (232).
Regarding claim 2, Yang teaches the structure of claim 1 and goes on to teach wherein the gate structure (GS, Fig 13) comprises p-GaN material (GaN, doped gallium nitride, [0016]) and the gate metal (232) is self-aligned (shown self-aligned; self-aligned, [0022]) to the p-GaN material (GaN).
Regarding claim 5, Yang teaches the structure of claim 1 and goes on to teach wherein the gate metal (232, Fig 13) is offset (shown offset) from edges (222SW) of the gate structure (GS) by a thickness (W1: maximum horizontal width of 224) of the inner sidewall spacers (224).
Regarding claim 6, Yang teaches the structure of claim 5 and goes on to teach further comprising an outer spacer (226, Fig 13) on (shown on) the inner sidewall spacers (224).
Regarding claim 7, Yang teaches the structure of claim 6 and goes on to teach wherein the outer spacer (226, Fig 13) comprise a passivation material (AlN, [0023]) on (shown on) a sidewall (228SW: inner sidewalls of 228) of a trench (228T: trench in 228 that accommodates 208/222/232/226/224) in dielectric material (228; dielectric material, [0023]), and
the inner sidewall spacers (224) are on (shown on) an inner surface (226SW: inner sidewalls of 226) of the outer spacer (226) in the trench (228T).
Regarding claim 8, Yang teaches the structure of claim 7 and goes on to teach wherein the gate metal (232, Fig 13) is within (shown within) the trench (228T) and extends (shown extended) to the gate structure (GS).
Regarding claim 9, Yang teaches the structure of claim 7 and goes on to teach wherein the gate metal (232, Fig 13) comprises a horizontal portion (232HP: top horizontal portions on left and right sides of 232 above 228) that is over (shown over) the outer spacer (226) and the inner sidewall spacers (224).
Regarding claim 10, Yang teaches the structure of claim 5 and goes on to teach wherein the outer spacer (226, Fig 13) comprises a passivation material (SiO2, [0023]) that extends (shown extended) onto (shown on) an edge (208SW: outermost sidewall of 208) of the gate structure (GS) underneath (shown under) the inner sidewall spacers (224), and over (shown over) the semiconductor substrate (Sub).
Regarding claim 11, Yang teaches the structure of claim 1 and goes on to teach wherein the gate metal (232, Fig 13) is symmetrically positioned over (shown symmetrically positioned over) the gate structure (GS).
Regarding claim 12, Yang teaches the structure of claim 1 and goes on to teach wherein the semiconductor substrate (Sub, Fig 13) comprises a wide-bandgap (wide-bandgap, [0002]) semiconductor stack of materials (wide-bandgap materials, [0017]).
Regarding claim 13, Yang teaches a structure (Fig 13), comprising:
wide-bandgap semiconductor layers (WBG: layers 203/204/206) formed on (shown on) a semiconductor substrate (202);
a device (HEMT, [0015]) including a gate structure (GS: layers 208/222) over (shown over) the wide-bandgap semiconductor layers (WBG);
a dielectric material (228; dielectric material, [0023]) over (shown over) the semiconductor substrate (202), the dielectric material (228) comprising a trench (228T: trench in 228 that accommodates 208/222/232/226/224) over (shown over) the device (HEMT);
inner sidewall spacers (224) over (shown over) the gate structure (GS) of the device (HEMT) and on sidewalls (228SW: inner sidewalls of 228) of the trench (228T); and
a gate metal (232) extending within (shown extended within) the trench (228T) and connecting (shown connected) to the device (HEMT), the gate metal (232) being surrounded (shown surrounded) by the inner sidewall spacers (224).
Regarding claim 14, Yang teaches the structure of claim 13 and goes on to teach wherein the gate metal (232, Fig 13) is symmetrically offset (208a; shown symmetrically offset) from edges (222SW: sidewall edges of 222) of the device (HEMT).
Regarding claim 15, Yang teaches the structure of claim 14 and goes on to teach wherein the offset (208a, Fig 13) is a thickness (W1: maximum horizontal width of 224) of the inner sidewall spacers (224).
Regarding claim 16, Yang teaches the structure of claim 13 and goes on to teach further comprising a passivation layer (226, Fig 13) over (shown over) the inner sidewall spacers (224).
Regarding claim 17, Yang teaches the structure of claim 16 and goes on to teach wherein the gate metal (232, Fig 13) extends over (shown extended over) the passivation layer (226) and the inner sidewall spacers (224).
Regarding claim 18, Yang teaches the structure of claim 16 and goes on to teach wherein the passivation layer (226, Fig 13) is under (shown under) the inner sidewall spacers (224) at the offset (208a).
Regarding claim 19, Yang teaches the structure of claim 13 and goes on to teach wherein the device (HEMT, Fig 13) comprises a p-GaN gate structure (208; GaN, doped gallium nitride, [0016]).
Regarding claim 20, Yang teaches a method comprising:
forming a gate structure (GS: layers 208/222, Fig 13) on (shown on) a semiconductor substrate (202);
forming inner sidewall spacers (224) on (shown on) an upper surface (222T: top surface of 222) of the gate structure (GS); and
forming a gate metal (232) connecting (shown connected) to the gate structure (GS) surrounded (shown surrounded) by sidewall spacers (224) and offset (shown offset) from edges (222SW: sidewall edges of 222) of the gate structure (GS).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3 and 4 are rejected under 35 U.S.C. 103 as being unpatentable over Yang (US 20220310824 A1), and further in view of Chou (US 20230299169 A1).
Regarding claims 3 and 4, Yang teaches the structure of claim 1 and the inner sidewall spacers (224, Fig 13).
Yang fails to explicitly teach the inner sidewall spacers comprise a dielectric material and the inner sidewall spacers comprise layers of dielectric material.
However, Chou teaches the inner sidewall spacers comprise layers (multilayer structure, [0038]) of dielectric material (SiO2, silicon oxide, [0038]).
Yang and Chou are considered analogous to the claimed invention because both are from the same field of endeavor of HEMT semiconductor devices. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the device of Yang with the features of Chou to create a structure wherein the inner sidewall spacers comprise a dielectric material and the inner sidewall spacers comprise layers of dielectric material thereby reducing the electric field at the edge of the gate structure. Therefore, the breakdown voltage of the HEMT device can be increased and the leakage current of the HEMT device can be reduced, thereby effectively improving the reliability of the HEMT device; and the edge portion of the gate structure can have a smaller thickness. In this way, the concentration of two-dimensional electron gas of the HEMT device can be increased, thereby improving the turn-on current and electrical performance (Chou, [0025]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Sung (US 20190348509 A1) - Gate electrode with overhang above spacers
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/JEREMY DANIEL WATTS/Examiner, Art Unit 2897 /CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
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