CTNF 18/427,051 CTNF 85158 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Specification 06-11 AIA The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. Claim Rejections - 35 USC § 102 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-12-aia AIA (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 07-15-03-aia AIA Claim s 1-9 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Lu (9711474) . PNG media_image1.png 514 841 media_image1.png Greyscale Regarding claim 1, Lu teaches a semiconductor package comprising: a substrate (70) comprising a first surface and a second surface, wherein the second surface is disposed in an opposite direction to the first surface (please see figure above); a semiconductor chip (10) on one of the first surface or the second surface; a first electronic device (51) on the second surface; a first molding layer (44) on the first surface; and a second molding layer (52’) on the second surface, wherein the second molding layer comprises an first open hole that exposes at least a portion of the first electronic device to an outside (please see 52’ which cover all but the top center of 51), and wherein a material of the second molding layer is located on at least a portion of an inner surface of the first open hole (please see 52’ showing this limitation). Regarding claim 2, Lu teaches a semiconductor package of claim 1, wherein the first open hole is disposed in an area of the second molding layer corresponding to a position of an external electrode (63) of the first electronic device. Regarding claim 3, Lu teaches a semiconductor package of claim 2, wherein a connection terminal (65) is disposed in an inner area of the first open hole. Regarding claim 4, Lu teaches a semiconductor package of claim 3, wherein the connection terminal is connected to the external electrode (please see figure above). Regarding claim 5, Lu teaches a semiconductor package of claim 3, wherein a gap is formed between the inner surface of the first open hole and an outer surface of the connection terminal (please see gap between 52’). Regarding claim 6, Lu teaches a semiconductor package of claim 1, wherein the second surface comprises: a central area; and a first edge area, a second edge area, a third edge area, and a fourth edge area, wherein the first edge area, the second edge area, the third edge area, and the fourth edge area form an outer circumference of the central area, wherein the first edge area is on a side of the substrate opposite from the third edge area, with the central area therebetween, and wherein the second edge area is on a side of the substrate opposite from the fourth edge area, with the central area therebetween (please see figure 6 above which shows this limitation). Regarding claim 7, Lu teaches a semiconductor package of claim 6, wherein one or more electronic devices, including the first electronic device, are disposed in the first edge area, the second edge area, the third edge area, and the fourth edge area (please see figure 6 above which shows this limitation). Regarding claim 8, Lu teaches a semiconductor package of claim 6, wherein one or more electronic devices, including the first electronic device, are disposed in areas of the second surface in which the first edge area, the second edge area, the third edge area and the fourth edge area overlap each other (please see figure 6 above which shows this limitation). Regarding claim 9, Lu teaches a semiconductor package of claim 6, wherein one or more electronic devices, including the first electronic device, are disposed in the central area (please see figure 6 above which shows this limitation) . 07-15-03-aia AIA Claim s 1 and 12-14 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Meyer (12237305) . PNG media_image2.png 365 604 media_image2.png Greyscale Regarding claim 1, Meyer teaches a semiconductor package comprising: a substrate (310b) comprising a first surface and a second surface, wherein the second surface is disposed in an opposite direction to the first surface (please see figure above); a semiconductor chip (326) on one of the first surface or the second surface; a first electronic device (602+ 604) on the second surface; a first molding layer (334) on the first surface; and a second molding layer (324) on the second surface, wherein the second molding layer comprises an first open hole (please see figure 6 which shows holes in 324 device 602 extrudes from) that exposes at least a portion of the first electronic device to an outside (please see figure 6 above), and wherein a material of the second molding layer is located on at least a portion of an inner surface of the first open hole (please see 324 having this detail). Regarding claim 12, Meyer teaches a semiconductor package of claim 1, wherein the first electronic device comprises: a body (602); a first external electrode (604); and a second external electrode (604), and wherein the first external electrode and the second external electrode are disposed on an outer surface of the body. Regarding claim 13, Meyer teaches a semiconductor package of claim 1, wherein the first electronic device comprises: a body (602); a first external electrode (604); a second external electrode (604); a third external electrode (604); and a fourth external electrode (604), wherein the first external electrode, the second external electrode, the third external electrode, and the fourth external electrode are disposed on an outer surface of the body, wherein the second molding layer further comprises a second open hole that exposes at least a portion of the first electronic device to the outside, and wherein the first open hole and the second open hole are formed in an area of the second molding layer corresponding to a position of the first electronic device (please see figure 6 above). Regarding claim 14, Meyer teaches a semiconductor package of claim 1, wherein the first electronic device comprises: a body (602); a first external electrode (604); a second external electrode (604); and a third external electrode (604), wherein the first external electrode, the second external electrode, and the third external electrode are disposed on an outer surface of the body, wherein the second molding layer further comprises a second open hole that exposes at least a portion of the first electronic device to the outside, and wherein the first open hole and the second open hole are formed in an area of the second molding layer corresponding to a position of the first electronic device (please see figure 6 above) . 07-15-03-aia AIA Claim s 15, 17 and 18 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Huang (20210013191) . PNG media_image3.png 384 723 media_image3.png Greyscale Regarding claim 15, Huang teaches a semiconductor package comprising: a substrate (DI) comprising a first surface and a second surface, wherein the second surface is disposed in an opposite direction to the first surface (please see figure above); a first semiconductor chip (200a) on the first surface; a second semiconductor chip (200b) on the second surface; a first electronic device (910) on the first surface; a second electronic device (920) on the second surface; a first molding layer (208) on the first surface; and a second molding layer (108) on the second surface, wherein the second molding layer comprises a first open hole (please see holes wherein 910 and 920 reside) that exposes at least a portion of the second electronic device to an outside (please bottom of 920 not being covered by 108), wherein a material of the second molding layer is located on at least a portion of an inner surface of the first open hole (please see portions of 108 within the layer 108), and wherein a connection terminal (951/952) connected to an external electrode (915/925) of the second electronic device is disposed inside the first open hole. Regarding claim 17, Huang teaches a semiconductor package of claim 15, wherein the external electrode of the second electronic device comprises a first external electrode, a second external electrode, a third external electrode, and a fourth external electrode, wherein the second molding layer further comprises a second open hole that exposes at least a portion of the second electronic device to the outside, and wherein the first open hole and the second open hole are formed in an area of the second molding layer corresponding to a position of the second electronic device (please see figure 10 above). Regarding claim 18, Huang teaches a semiconductor package of claim 15, wherein the external electrode of the second electronic device comprises a first external electrode, a second external electrode, and a third external electrode, wherein the second molding layer further comprises a second open hole that exposes at least a portion of the second electronic device to the outside, and wherein the first open hole and the second open hole are formed in an area of the second molding layer corresponding to a position of the second electronic device (please see figure 10 above) . 07-15-03-aia AIA Claim s 19 and 20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Huang (20210013191) . PNG media_image3.png 384 723 media_image3.png Greyscale Regarding claim 19, Huang teaches a semiconductor assembly comprising: a main substrate (202); and a semiconductor package (90b’) mounted on the main substrate, wherein the semiconductor package comprises: a substrate (DI) comprising a first surface and a second surface, wherein the second surface is disposed in an opposite direction to the first surface (please see figure 10 above); a first semiconductor chip (100) on the first surface; a second semiconductor chip (910) on the second surface; a first electronic device (110) on the first surface; a second electronic device (920) on the second surface; a first molding layer (208) on the first surface; and a second molding layer (108) on the second surface, wherein the second molding layer comprises an open hole (please see holes wherein 910 and 920 reside) that exposes at least a portion of the second electronic device to an outside (please bottom of 920 not being covered by 108), wherein a material of the second molding layer is located on at least a portion of an inner surface of the open hole (please see portions of 108 within the layer 108), and wherein a connection terminal (951/952) connected to an external electrode (915/925) of the second electronic device is disposed inside the first open hole. Regarding claim 20, Huang teaches a semiconductor assembly of claim 19, further comprising an underfill molding layer (206) disposed between the semiconductor package and the main substrate . Allowable Subject Matter 12-151-08 AIA 07-43 12-51-08 Claim 10 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. 12-151-08 AIA 07-43 12-51-08 Claim 11 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. 12-151-08 AIA 07-43 12-51-08 Claim 16 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to CALEB E HENRY whose telephone number is (571)270-5370. The examiner can normally be reached Mon-Fri. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at (571) 270-3829 . The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /CALEB E HENRY/Primary Examiner, Art Unit 2818 Application/Control Number: 18/427,051 Page 2 Art Unit: 2818 Application/Control Number: 18/427,051 Page 3 Art Unit: 2818 Application/Control Number: 18/427,051 Page 4 Art Unit: 2818 Application/Control Number: 18/427,051 Page 5 Art Unit: 2818 Application/Control Number: 18/427,051 Page 6 Art Unit: 2818 Application/Control Number: 18/427,051 Page 7 Art Unit: 2818 Application/Control Number: 18/427,051 Page 8 Art Unit: 2818 Application/Control Number: 18/427,051 Page 9 Art Unit: 2818 Application/Control Number: 18/427,051 Page 10 Art Unit: 2818 Application/Control Number: 18/427,051 Page 11 Art Unit: 2818
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