DETAILED ACTION
This action is responsive to the following: the arguments made after non-final rejection filed on May 29, 2026.
Claims 1-20 are pending. Claims 1, 12, and 17 are independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 6, 10 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 20240021519) in view of Garcia et al (US 8320165).
Regarding Independent Claim 1, Kim teaches a device, comprising:
a memory macro (Fig 1: 10) having a frontside and a backside (para 44 “the first surface 100_S1 of the substrate 100 may be a frontside of the substrate 100, and the second surface 100_S2 of the substrate 100 may be a backside of the substrate 100.”) along a vertical direction, wherein the memory macro includes:
edge strap areas (Fig. 1: 22) extending lengthwise along a first direction at edges of the memory macro (Fig. 1: 10),
a memory cell area (Fig 1: 12) having a plurality of memory cells (Fig 1: 14), wherein the memory cell area is disposed between the edge strap areas (Fig. 1: 22) along a second direction perpendicular to the first direction, and
a feedthrough circuit (Fig. 4: THP1, THP3) that routes a power signal line (Fig. 4: PW_L1, PW_L2) of one of the plurality of memory cells to the backside (Fig. 4: BS_M12, BS_M11, BS_M13, 100_S2) of the memory macro (Fig. 1: 10).
Kim fails to teach a middle strap area.
Garcia teaches a middle strap area (Fig. 2: 2008) extending lengthwise along the first direction and disposed between the edge strap areas (Fig. 2: 2004, 2012) along the second direction, wherein the middle strap area divides the memory cell area (Fig. 2: 2002) into two memory cell domains.
For larger macros it would be advantageous to divide the memory array into sub domains separated by a middle strap area to provide more robust power distribution throughout the array and prevent signal degradation. This would be particularly useful in lower power macros where small amounts of signal loss due to IR drop could render the device inoperable.
It would therefore have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to apply the teachings of Garcia to the teachings of Kim to produce a memory macro with edge strap areas and a middle strap area that route power along the backside of the macro connecting to power by feedthrough circuits.
Regarding Claim 2, Kim and Garcia teach the limitations of Claim 1. Kim further teaches wherein the power signal line (Fig. 4: PW_L1, PW_L2) is connected to a high voltage power supply Vdd (para 155 “The first rear wiring line BS_M11 may be, for example, a high power line PW_L1.”) or to a low voltage power supply Vss (para 156 “f the second rear wiring line BS_M12 and the third rear wiring line BS_M13 may be a low power line PW_L2.”).
Regarding Claim 3, Kim and Garcia teach the limitations of Claim 1. Kim further teaches wherein the edge strap areas (fig. 1: 22) also include feedthrough circuits (Fig. 4: THP1, THP3) that routes the power signal line (Fig. 4: BS_M11, BS_M12, BS_M13) of the one of the plurality of memory cells to the backside (Fig. 4: 100_S2) of the memory macro (Fig. 1: 10).
Regarding Claim 6, Kim and Garcia teach the limitations of Claim 1. Kim further teaches a backside metal line (Fig. 4: BS_M11, BS_M12, BS_M13) disposed on the backside (Fig. 4: 100_S2) of the memory macro (Fig. 1: 10), wherein a feedthrough via (Fig. 4: THP1, THP2, THP3) of the feedthrough circuit lands on the backside metal line.
Regarding claim 10, Kim and Garcia teach the limitations of Claim 1.
Kim and Garcia are silent with respect to the specific provision of the memory cell arear having 512 SRAM cells and each of the two memory cell domains has 256 SRAM cells. Kim and Garcia do not mention any details about the capacity of their memory arrays.
An SRAM cell is a basic unit of storage for one data bit, in the form of logic low (i.e., “0” or Vss) or logic high (i.e., “1” or Vdd). The quantity of SRAM cells is indicative of the quantity of data that can be stored. Because one SRAM cell stores one bit of data, the total number of SRAM cells will equal the total storage capacity.
Each SRAM cell is addressable by a column and a row, indicated by a binary address. In other words, the number of addressable memory cells must be powers of base 2 (e.g., 2, 4, 8, 16, 32, 64, 128, 256, 512 . . .).
The only difference between the claimed memory and the prior art memory is the provision of a different capacity of 512 memory cells. If anything, this claim merely represents an unpatentable change in size--the size or capacity of data storage--, because the claimed SRAM memory would not perform differently than the prior art memory. Applicant’s originally filed Specification merely uses the capacity as an example, placing no patentable significance on the size (see e.g., Spec. para. 27: “The memory macro 200 includes memory cell areas 102 having arrays of memory cells 104 that store memory bits (e.g., 512 SRAM cells for storing 512 bits).”; see also Spec. para 48: “Referring to the embodiment in Fig. 9A, the memory macro 200 has N bits where N is 512. . . . However, N may be any other number (e.g., 256, 1024) depending on design requirements.”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to appreciate the teachings of Kim and Garcia are for SRAM in general, regardless of size or capacity, and to change the size of the SRAM array (or i.e., quantity of SRAM cells). See MPEP 2144.04(IV)(A).
Regarding Claim 11, Kim and Garcia teach the limitations of Claim 1. Garcia further teaches wherein the middle strap area (Fig. 2: 2008) is a first middle strap area, and the memory macro further includes additional middle strap areas extending lengthwise along the first direction and disposed between the edge strap areas along the second direction, the additional middle strap areas (Fig. 2: 2004, 2006, 2010, 2012) divides the memory cell area (Fig. 2: 2002) into additional memory cell domains, wherein each of the additional middle strap areas include a feedthrough circuit that routes a power signal line of one of the plurality of memory cells to the backside of the memory macro.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 20240021519) and Garcia et al (US 8320165) in view of Lee et al (US 20230389258).
Regarding Claim 4, Kim and Garcia teach the limitations of Claim 1. Kim and Garcia fail to teach a logic circuit area adjacent the memory macro, wherein the logic circuit area is isolated from the memory cell area by one of the edge strap areas.
Lee teaches a logic circuit area (Fig. 1: 13, 14) adjacent the memory macro (Fig. 1: 11), wherein the logic circuit area is isolated from the memory cell area by one of the edge strap areas (Fig. 4: 18, 22).
Positioning logic adjacent to edge strap areas helps reduce noise that can interfere with operations performed on the cells.
It would therefore have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to apply the teachings of Lee to the teachings of Kim and Garcia to produce a memory device where there are logic circuits adjacent the memory macro but separated from the memory cells by the edge strap cells.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 20240021519) (hereafter referred to as Kim ‘519), Garcia et al (US 8320165), and Lee et al (US 20230389258) in view of Kim et al (US 20180130818) (hereafter referred to as Kim ‘818).
Kim ‘519, Garcia, and Lee teach the limitations of Claim 4.
Lee teaches wherein the one of the edge strap areas (Fig. 4: 18, 22) spans between the memory macro (Fig. 4: 12) and the logic circuit area (Fig. 1: 13, 14).
Kim ‘519, Garcia and lee fail to teach that the middle strap area is wider than the edge strap area.
Kim ‘818 teaches the middle strap area spans a greater width along the second direction than the edge strap areas (Fig 1 shows a DCR and WCTR on each edge of the macro and a DCR and two WCTR in the middle of the macro. It stands to reason that the middle strap area is wider than the edge areas.).
A wider middle strap area than edge strap areas is obviously advantageous because the middle area abuts memory subarrays on two sides and thus would need to be larger in order to effectively send sufficient power or signals to the adjacent arrays whereas edge straps only abut memory cells on one side.
It would therefore have been obvious to one of ordinary kill in the art prior to the filing date of the claimed invention to apply the teachings of Kim ‘818 to the teachings of Kim ‘519, Garcia, and Lee for the reasons stated above.
Regarding Claim 19, Kim, and Garcia, and Lee teach the limitations of Claim 17.
Claim 19 is rejected for the same reasons as claim 5.
Claims 12, 14-16 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 20240021519) (hereafter referred to as Kim ‘519) in view of Garcia et al (US 8320165) and Kim et al (US 20180130818) (hereafter referred to as Kim ‘818).
Regarding Independent Claim 12, Kim ‘519 teaches a device, comprising:
a memory macro (Fig 1: 10) having a frontside and a backside (para 44 “the first surface 100_S1 of the substrate 100 may be a frontside of the substrate 100, and the second surface 100_S2 of the substrate 100 may be a backside of the substrate 100.”) along a vertical direction, wherein the memory macro includes:
a memory cell area (Fig 1: 12) having a plurality of memory cells (Fig 1: 14),
an edge strap area (Fig. 1: 22) adjacent a first side of the memory cell area (Fig. 1: 12), the edge strap area extending lengthwise along a first direction at an edge of the memory macro, and
a feedthrough circuit (Fig. 4: THP1, THP3) that routes a power signal line (Fig. 4: PW_L1, PW_L2) of one of the plurality of memory cells to a backside (Fig. 4: BS_M12, BS_M11, BS_M13, 100_S2) of the memory macro (Fig. 1: 10),
However, Kim ‘519 fails to teach a middle strap area.
Garcia teaches a middle strap area (Fig. 2: 2008) within the memory cell area, the middle strap area extending lengthwise along the first direction, wherein the middle strap area divides the memory cell area (Fig. 2: 2002) into two memory cell domains,
Garcia and Kim ‘519 both fail to teach the middle strap area is wider than the edge strap areas.
further teaches wherein the middle strap area spans a first width along a second direction perpendicular to the first direction, the edge strap area spans a second width along the second direction, the first width is a distance between the two memory cell domains, and the first width is greater than the second width.
Kim ‘818 teaches the middle strap area spans a greater width along the second direction than the edge strap areas (Fig 1 shows a DCR and WCTR on each edge of the macro and a DCR and two WCTR in the middle of the macro. It stands to reason that the middle strap area is wider than the edge areas.).
For larger macros it would be advantageous to divide the memory array into sub domains separated by a middle strap area to provide more robust power distribution throughout the array and prevent signal degradation. This would be particularly useful in lower power macros where small amounts of signal loss due to IR drop could render the device inoperable.
A wider middle strap area than edge strap areas is obviously advantageous because the middle area abuts memory subarrays on two sides and thus would need to be larger in order to effectively send sufficient power or signals to the adjacent arrays whereas edge straps only abut memory cells on one side.
It would therefore have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to apply the teachings of Garcia to the teachings of Kim to produce a memory macro with edge strap areas and a middle strap area that route power along the backside of the macro connecting to power by feedthrough circuits. Where the middle strap area is wider than the edge strap areas.
Regarding Claim 14, Kim ‘519, Garcia, and Kim ‘818 teach the limitations of Claim 12.
Kim ‘818 further teaches the edge strap area is a first edge strap area (Fig. 1: WCTR; left side of the array), further comprising:
a second edge strap area (Fig. 1: WCTR; right side of the array) adjacent a second side of the memory cell area (Fig. 1: CAR; right side of the array), the second edge strap area (Fig. 1: WCTR; right side of the array) extending lengthwise along the first direction at a second edge of the memory macro;
a first logic circuit area (Fig. 1: DCR; left side of the array) adjacent a first side of the memory macro, wherein the first logic circuit area is isolated from the memory cell area (Fig. 1: CAR; left side of the array) by the first edge strap area (Fig. 1: WCTR; left side of the array); and
a second logic circuit area (Fig. 1: DCR; right side of the array) adjacent a second side of the memory macro, wherein the second logic circuit area is isolated from the memory cell area (Fig. 1: CAR; right side of the array) by the second edge strap area (Fig. 1: WCTR; right side of the array).
Regarding Claim 15, Kim ‘519, Garcia, and Kim ‘818 teach the limitations of Claim 12. Kim ‘519 further teaches wherein the power signal line (Fig. 4: PW_L1, PW_L2) is connected to a high voltage power supply VDD (para 155 “The first rear wiring line BS_M11 may be, for example, a high power line PW_L1.”) or to a low voltage power supply VSS (para 156 “f the second rear wiring line BS_M12 and the third rear wiring line BS_M13 may be a low power line PW_L2.”).
Regarding Claim 16, Kim ‘519, Garcia, and Kim ‘818 teach the limitations of Claim 12. Kim ‘519 further teaches wherein the middle and edge strap areas do not include memory cells (para 36 “The edge straps 18 and 22 may not be designed to function as the SRAM unit cells 14, but may be a circuit area designed to provide other functions.”).
Claims 13 is rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 20240021519) (hereafter referred to as Kim ‘519), Garcia et al (US 8320165), and Kim et al (US 20180130818) (hereafter referred to as Kim ‘818) in view of Lee et al (US 20230389258).
Regarding Claim 13, Kim ‘519, Garcia, and Kim ‘818 teach the limitations of Claim 12.
Garcia teaches a second logic circuit (Fig. 2: 2024) adjacent a second side of the memory macro (Fig. 2: 2002), wherein the second logic circuit directly abuts the memory cell area without an intervening edge strap area.
Garcia, Kim ‘519, and Kim ‘818 fail to teach adjacent logic to the memory array separated by edge cells.
Lee teaches a first logic circuit (Fig. 1: 13) area adjacent a first side (Fig. 2: 22) of the memory macro (Fig. 2: 10), wherein the first logic circuit area is isolated from the memory cell area by the edge strap area (Fig. 2: 22);
Positioning logic adjacent to edge strap areas helps reduce noise that can interfere with operations performed on the cells.
It would therefore have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to apply the teachings of Lee to the teachings of Kim and Garcia to produce a memory device where there are logic circuits adjacent the memory macro but separated from the memory cells by the edge strap cells.
Claims 17-18, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 20240021519) in view of Garcia et al (US 8320165) and Lee et al (US 20230389258).
Regarding Independent Claim 17, Kim teaches a device, comprising:
a memory macro (Fig 1: 10) having a plurality of memory cells (Fig 1: 14), the memory macro having a frontside and a backside (para 44 “the first surface 100_S1 of the substrate 100 may be a frontside of the substrate 100, and the second surface 100_S2 of the substrate 100 may be a backside of the substrate 100.”);
vertical metal routing (Fig. 4: THP1, THP2, THP3) that electrically connect to a power signal line (Fig. 4: PW_L1, PW_L2) of one of the plurality of memory cells to a backside (Fig. 4: BS_M12, BS_M11, BS_M13, 100_S2) of the memory macro (Fig. 1: 10);
edge strap areas (Fig. 1: 22) on edges of the memory macro (Fig. 1: 10), wherein the edge strap areas also include vertical metal routing (Fig. 4: THP1, THP2, THP3) that electrically connect to the power signal line (Fig. 4: PW_L1, PW_L2) of the one of the plurality of memory cells to a backside (Fig. 4: BS_M12, BS_M11, BS_M13, 100_S2) of the memory macro (Fig. 1: 10); and
Kim fails to teach logic adjacent to the memory cells.
Lee teaches logic circuit areas adjacent (Fig. 1: 13) the memory macro (Fig 1. 11), the logic circuit areas having a plurality of logic cells adjacent the edge strap areas (Fig. 2: 22), wherein the logic cells and the memory cells have active regions with different configurations.
Kim and Lee fail to teach a middle strap area.
Garcia a middle strap area (Fig. 2: 2008) disposed between two memory cells (Fig. 2: 2014) of the plurality of memory cells
Positioning logic adjacent to edge strap areas helps reduce noise that can interfere with operations performed on the cells.
For larger macros it would be advantageous to divide the memory array into sub domains separated by a middle strap area to provide more robust power distribution throughout the array and prevent signal degradation. This would be particularly useful in lower power macros where small amounts of signal loss due to IR drop could render the device inoperable.
It would therefore have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to apply the teachings of Garcia to the teachings of Kim to produce a memory macro with edge strap areas and a middle strap area that route power along the backside of the macro connecting to power by vertical metal routing. That has logic cell areas adjacent to the edge cell areas.
Regarding Claim 18, Kim, Garcia, and Lee teach the limitations of Claim 17. Lee further teaches wherein in the memory cells, the active regions (Fig. 4: AP1-6) for p-type transistors (Fig. 3: PU1, PU2) and n-type transistors (Fig. 3: PD1, PD4, PG1-4) extend lengthwise along a first direction at different lengths,
wherein in the logic cells, active regions for p-type transistors and n-type transistors extend lengthwise along the first direction at same lengths (para 29 “The input/output (I/O) block 13 may include a bit line precharge circuit, a column driver, a read circuit, and a write circuit, according to some embodiments.” It is understood to one skilled in the art that such circuits would require n-type and p-type transistors and active regions.).
Regarding Claim 20, Kim, Garcia, and Lee teach the limitations of Claim 17. Garcia further teaches wherein the middle strap area (Fig. 2: 2008) is a first middle strap area, and the memory macro further includes additional middle strap areas extending lengthwise along the first direction and disposed between the edge strap areas along the second direction, the additional middle strap areas (Fig. 2: 2004, 2006, 2010, 2012) divides the memory cell area (Fig. 2: 2002) into additional memory cell domains, wherein each of the additional middle strap areas include a feedthrough circuit that routes a power signal line of one of the plurality of memory cells to the backside of the memory macro.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 20240021519) (hereafter referred to as Kim ‘519), Garcia et al (US 8320165), and Lee et al (US 20230389258) in view of Kim et al (US 20180130818) (hereafter referred to as Kim ‘818).
Kim ‘519, Garcia, and Lee teach the limitations of Claim 17.
Lee teaches wherein the one of the edge strap areas (Fig. 4: 18, 22) spans between the memory macro (Fig. 4: 12) and the logic circuit area (Fig. 1: 13, 14).
Kim ‘519, Garcia and lee fail to teach that the middle strap area is wider than the edge strap area.
Kim ‘818 teaches the middle strap area spans a greater width along the second direction than the edge strap areas (Fig 1 shows a DCR and WCTR on each edge of the macro and a DCR and two WCTR in the middle of the macro. It stands to reason that the middle strap area is wider than the edge areas.).
A wider middle strap area than edge strap areas is obviously advantageous because the middle area abuts memory subarrays on two sides and thus would need to be larger in order to effectively send sufficient power or signals to the adjacent arrays whereas edge straps only abut memory cells on one side.
It would therefore have been obvious to one of ordinary kill in the art prior to the filing date of the claimed invention to apply the teachings of Kim ‘818 to the teachings of Kim ‘519, Garcia, and Lee for the reasons stated above.
Allowable Subject Matter
Claims 7-10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 7 teaches the structure of the power signal line for a memory cell in the array. Garcia, Kim ‘818, Kim ‘519, and Lee fail to teach the specific structure outlined in this claim. It would there for be allowable if written in independent form.
Response to Arguments
Applicant's arguments filed February 10, 2026 have been fully considered but they are not persuasive.
In response to applicant's argument that the examiner's conclusion of obviousness is based upon improper hindsight reasoning, it must be recognized that any judgment on obviousness is in a sense necessarily a reconstruction based upon hindsight reasoning. But so long as it takes into account only knowledge which was within the level of ordinary skill at the time the claimed invention was made, and does not include knowledge gleaned only from the applicant's disclosure, such a reconstruction is proper. See In re McLaughlin, 443 F.2d 1392, 170 USPQ 209 (CCPA 1971).
Applicant arguments toward Claims 1, 12, and 17 seem to largely be arguing against the references individually rather than the combination of references. In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
For these reasons the rejections under 35 U.S.C. 103 are maintained.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/JOSEPH FIDELIS STORMES/Examiner, Art Unit 2825
/ALEXANDER SOFOCLEOUS/Supervisory Patent Examiner, Art Unit 2825
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