CTNF 18/427,328 CTNF 85098 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Priority Acknowledgment is made of applicant's claim for foreign priority under 35 U.S.C. 119(a)-(d). Information Disclosure Statement The information disclosure statements filed on 1/30/2024, 6/6/2024, and 1/23/2025 have been acknowledged and signed copies of the PTO-1449 are attached herein. Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 1,2, 14, 15, 16, 18, 19 and 26 are rejected under 35 U.S.C. 103 as being unpatentable over Shin et al. (US 2022/0399529, hereinafter “Shin”) in view of Kawano et al. (US 2012/0127064, hereinafter “Kawano”) . In regards to claim 1, Shin discloses (See, for example, Fig. 1 and 14) a display panel comprising (10) : a plurality of pixel blocks (110) including a plurality of subpixels (1SP1, 1SP2, 1SP3, 2SP1, 2SP2, 2SP3, See, for example, Fig. 2A) disposed in a display area (10) ; a bezel area disposed outside the display area (See, Pars [0059], [0060], and [0061]) ; and a plurality of mode control line sets (EM2, EM3) individually connected to the plurality of pixel blocks (See, for example, Par [0257]) , wherein each of the plurality of mode control line sets includes a first mode control line (EM2) for supplying a first mode control signal and a second mode control line (EM3) for supplying a second mode control signal (See, Pars [0262]-[0265]) , and wherein each of the plurality of subpixels (SP, See Fig. 9) includes: a first lens region (Lz1) disposed on the first light emitting device (OLED1) ; and a second lens region (Lz2) disposed on the second light emitting device (OLED2) , wherein the first lens region (Lz1) and the second lens region (Lz2) differently control a viewing angle in a first direction (wide-angle, narrow-angle, See Fig. 9) . However, Shin is silent about a driving transistor connected to a first power line; a first light emitting device connected to the driving transistor through a first mode control transistor controlled by the first mode control signal; a second light emitting device connected to the driving transistor through a second mode control transistor controlled by the second mode control signal. Kawano while disclosing an organic electroluminescent display apparatus teaches (See, for example, Fig. 8) a driving transistor (M2) connected to a first power line (“POWER SUPPLY POTENTIAL”) ; a first light emitting device (A) connected to the driving transistor (M2) through a first mode control transistor (M3) controlled by the first mode control signal (P2) ; a second light emitting device (B) connected to the driving transistor (M2) through a second mode control transistor (M4) controlled by the second mode control signal (P3) . Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to modify the pixel circuit of Shin with the dual-mode pixel circuit of Kawano because this would help reduce circuit complexity while enabling selective driving of the wide-angle and narrow-angle light emitting devices from a single data signal. In regards to claim 2, Shin as modified above discloses (See, for example, Fig. 11) each subpixel (SP) controls the viewing angle of the first direction to a wide viewing angle (WAA) through the first lens region (Lz1) by driving the first light emitting device (OLED1) when the first mode control signal is activated (See, for example, Par [0197]) , and each subpixel (SP) controls the viewing angle of the first direction to a narrow viewing angle (NAA) through the second lens region (Lz2) by driving the second light emitting device (OLED2) when the second mode control signal is activated (See, for example, Pars [0198]-[0199]) . In regards to claim 14, Shin as modified above discloses (See, for example, Fig. 12) wherein each subpixel (Par [0204]) includes: a storage capacitor connected to a gate electrode of the driving transistor (a storage capacitor Cst connected to the gate of the driving transistor Tdr, Par [0215]) ; a first switching transistor (T1) configured to supply a data voltage of a data line (Vdata) to a first electrode (Cst electrode at node P1) of the storage capacitor in response to a first scan signal of a first gate line (a first switch transistor T1 supplying data voltage Vdata from the date line to node P1 as the first electrode of Cst in response to first scan signal SCAN1 from the first gate line 15a, See Par [0216]) ; a second switching transistor (T2) configured to connect the driving transistor (Tdr) in a diode structure in response to a second scan signal (SCAN2) of a second gate line (15b) (a second switch transistor T2 connecting the driving transistor in a diode structure in response to second scan signal SCAN2 from second gate line 15b, See Par [0217]) ; a third switching transistor (T3) configured to supply an initialization voltage (Vref) of an initialization voltage line to the first electrode of the storage capacitor (Cst) in response to an emission control signal of a third gate line (a third switch transistor T3 supplying reference voltage Vref from a reference line to node P1 in response to light-emitting signal EM1 from third gate line 15c, Par [0220]) ; a fourth switching transistor (T4) configured to connect the driving transistor (Tdr) and the first and second mode control transistors in response to the emission control signal of the third gate line (a fourth switch transistor T4 as a first light-emission control thin-film transistor and a sixth switch transistor T6 as a second light-emission control thin-film transistor connecting the driving transistor to the light emitting diodes in response to the light-emission control signals, See Pars [0221]-[0226]) ; a fifth switching transistor (T5) configured to supply the initialization voltage (Vref) of the initialization voltage line to an anode electrode of the second light emitting device (OLED1) in response to the second scan signal (SCAN2) of the second gate line (a fifth switch transistor T5 supplying the reference voltage to a node connected to the anode electrode in response to the second scan signal SCAN2, Par [0223]) ; and a seventh switching transistor (T7) configured to supply the initialization voltage (Vref) of the initialization voltage line to an anode electrode of the first light emitting device (OLED2) in response to the second scan signal (SCAN2) of the second gate line (a seventh switch transistor T7 supplying the reference voltage to a node connected to the anode electrode in response to the second scan signal SCAN2, Par [0226]). In regards to claim 15, Shin as modified above discloses (see, for example, Fig. 10) that wherein the first light emitting device includes a first light emitting area (OLED1) , and the first lens region includes a first lens (Lz1) which overlaps the first light emitting area and has a bottom surface (14µm) which is wider than a bottom surface of the first light emitting area (8.5µm, See for example, Pars [0176] and [0179]) . In regards to claim 16, Shin as modified above discloses (See, for example, Figs. 2A and 10) that wherein the second light emitting device includes a plurality of second light emitting areas (OLED2) , the second lens region includes a plurality of second lenses (Lz2) overlapped with the plurality of second light emitting areas (OLED2) , and each of the plurality of second lenses (Lz2) includes a bottom surface (16.5µm) which is wider than a bottom surface of each of at least one of the plurality of second light emitting areas (8.5µm, See, for example, Par [0189]) . In regards to claim 18, Shin as modified above discloses (See, for example, Fig. 3) that wherein the first lens region (Lz1) and the second lens region (Lz2) control the viewing angle identically in a second direction vertical to the first direction (the first lens Lz1 of semi-cylindrical shape does not cur off in the x-x’ direction while the second lens Lz2 of semi-spherical shape controls viewing in both x-x’ and y-y’ directions, where the first lens has minimal control in the x-x’ direction making the two lens regions’ control similar in that direction, See, for example, Pars [0133]-[0136]) . In regards to claim 19, shin as modified above discloses (See, for example, Fig. 3) wherein a first lens in (Lz1) the first lens region is a half-cylindrical lens (See, Par [0129]) elongated in the first direction, and a second lens (Lz2) in the second lens region is a half-spherical lens (See, Par [0129]) . In regards to claim 26, Shin as modified above discloses (See, for example, Figs. 1 and 14) a display apparatus comprising: the display panel of claim 1; and a data driver disposed in the bezel area and configured to drive data lines disposed in the display area (a display device 100 comprising the display panel 10 and a data driver 30 disposed in the bezel area for driving the date lines DL1 to DLm in the display region, See, for example, Pars [0056], [0059]-[0060]) , wherein the data driver individually supplies the first mode control signal and the second mode control signal to each of the plurality of mode control line sets (the timing controller 40 individually supplies the first light-emission control signal to the first light-emission control signal application line EM2 and the second light-emission control signal to the second light emission control signal application line EM3, See Pars [0267]-[0268]) . 07-22-aia AIA Claim s 3-9 are rejected under 35 U.S.C. 103 as being unpatentable over Shin in view of Kawano as applied to claim 1 above, and further in view of Ogawa et al. (US 2022/0157229, hereinafter “Ogawa”) . In regards to claim 3, Shin as modified above disclose all limitations of claim 1 except that wherein, in each of the plurality of pixel blocks, the first mode control line includes a first mode control line of a first type disposed in the first direction and a first mode control line of a second type disposed in a second direction different from the first direction, and the second mode control line includes a second mode control line of the first type disposed in the first direction and a second mode control line of the second type disposed in the second direction. Ogawa while disclosing a display device teaches (See, for example, Fig. 9) that wherein, in each of the plurality of pixel blocks (See, for example, 49) , the first mode control line includes a first mode control line of a first type (SG) disposed in the first direction (Dx) and a first mode control line of a second type (L2) disposed in a second direction (Dy) different from the first direction (Dx) , and the second mode control line includes a second mode control line of the first type (HG) disposed in the first direction (Dx) and a second mode control line of the second type (L1) disposed in the second direction (Dy) (See also, Pars [0108], [0112], [0114], and [0117]) . Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to modify the mode control line routing of Shin in view of Kawano with the two-directional segmented routing taught by Ogawa because it provides efficient connection to individual transistors within each pixel block while maintaining a compact pixel layout that enables high resolution display panels with multiple control signals per pixel block. In regards to claim 4, Shin as modified above discloses (See, for example, Fig. 9, Ogawa) that wherein the first mode control line of the first type (SG) and the second mode control line of the first type (HG) , which are disposed in any one pixel block among the plurality of pixel blocks, are separated from the first mode control line of the second type (L2) and the second mode control line of the second type (L1) disposed in another pixel block adjacent in the first direction (See also, for example, Fig. 1 and Pars [0059], [0108]) . In regards to claim 5, Shin as modified above discloses (See, for example, Figs. 1 and 9, Ogawa) that wherein the first mode control line of the second type (L2) and the second mode control line of the second type (L1) , which are disposed in any one pixel block among the plurality of pixel blocks, extend in the second direction (Dy) to other pixel blocks adjacent in the second direction (See, for example, Fig. 1, Pix and 49). In regards to claim 6, Shin as modified above discloses (See, for example, Figs. 1 and 9) that wherein, in each of the plurality of pixel blocks, the first mode control line of the second type (L2) and the second mode control line of the second type (L1) are disposed in parallel with a second power line (PVSS) between each of unit pixels and extend in the second direction (See, for example, Par [0108]) . In regards to claim 7, Shin as modified above discloses (See, for example, Fig. 9, Ogawa) that wherein, in each of the subpixels, a data line, an initialization voltage line, and the first power line connected to each subpixel extend in the second direction (See, for example, Par [0108]) . In regards to claim 8, Shin as modified above discloses (See, for example, Figs. 7 and 9) that wherein, in a first type pixel area included in each pixel block, the first mode control line of the first type (SG) and the first mode control line of the second type (L2) are connected to each other through a first contact hole of an insulating layer, and the second mode control line of the first type (HG) and the second mode control line of the second type (L1) are connected to each other through a second contact hole of an insulating layer (See, Pars [0088], and [0111]) . In regards to claim 9, Shin as modified above discloses (See, for example, Fig. 9) that wherein, in a second type pixel area included in each pixel block, the first mode control line of the first type (SG) intersects the first mode control line of the second type (L2) with an insulating layer interposed therebetween (insulating layers between gate and drain/source electrodes) , and the second mode control line of the first type (HG) intersects the second mode control line of the second type (L1) with an insulating layer interposed therebetween (insulating layers between gate and drain/source electrodes) . 07-22-aia AIA Claim s 11, 12, 22, 24 and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Shin in view of Kawano as applied to claim 1 above, and further in view of Ogawa, Kim (US 2011/0050660, hereinafter “Kim’660”) , and Kim (US 2013/0335397, hereinafter “Kim’397”) . In regards to claim 11, Shin as modified above discloses all limitations of claim 3 except that wherein each of the plurality of mode control line sets includes: a first mode control line of a third type and a second mode control line of a third type disposed in the bezel area; an electrostatic prevention circuit connected to each of the first mode control line of the third type and the second mode control line of the third type; and a lighting test circuit connected to the first mode control line of the third type and the second mode control line of the third type. Kim’660 while disclosing an organic light emitting display device teaches (See, for example, Figs. 1-2) wherein each of the plurality of mode control line sets includes: a first mode control line of a third type (TG) and a second mode control line of a third type (TD) disposed in the bezel area (a lighting testing circuit 160 disposed in the bezel area, where the lighting test circuit includes a plurality of transistors M1 to Mm connected to control lines including an input line of test control signal TG and an input line of lighting test signal TD disposed in the bezel area, Pars [0032], [0043]-[0046]) ; and a lighting test circuit (160) connected to the first mode control line of the third type (TG) and the second mode control line of the third type (TD) . Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to modify the display panel of Shin with the lighting test circuit of Kim’660 because this would help enable detection of defective panels before mounting of the driving IC to prevent unnecessary material consumption. Kim’397 while disclosing an organic light emitting diode teaches (See, for example, Figs. 6-9) an electrostatic prevention circuit connected to each of the first mode control line of the third type and the second mode control line of the third type (an electrostatic prevention circuit comprising a resistor R coupling the input line transmitting the test control signal TG to power supply line VGHL or VGLL for ESD protection, where this electrostatic prevention circuit is connected to control lines associated with a lighting test circuit 90 in the bezel area, See Pars [0112]-[0113]). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to further modify Shin by the electrostatic prevention circuit of Kim’397 because this would help protect the transistors of the lighting test circuit from damage caused by static electricity (ESD) during manufacturing and module-state operation. In regards to claim 12, Shin as modified above discloses (See, for example, Fig. 1-2, Kim’660) that wherein the first mode control line of the third type (TG) and the second mode control line of the third type (TD) are disposed in a data link area (140) disposed in the bezel area or are disposed outside (150) the data link area (140) . In regards to claim 22, Shin as modified above discloses (See, for example, Figs. 1 and 5, Kim’660) wherein a chip on film is disposed in the bezel region, and wherein the data link area is located between the chip on film and the display area (a driving IC 180 mounted in a chip form on the IC mounting region 150 in the bezel area, See, Par [0058]-[0059], with the data distribution circuit 140 located between the IC mounting region and the display area pixel unit 110). In regards to claim 24, Shin as modified above discloses (See, for example, Fig. 6, Kim’397) that wherein in an area corresponding to the electrostatic prevention circuit (See Pars [0112], [0113]) and the lighting test circuit (90) in the bezel area, a plurality of data input lines, the first and second mode control lines of the third type, and a plurality of power input lines (IL1, IL2) are disposed in parallel in the first direction and extend in the second direction (See, for example, Fig. 9) . In regards to claim 25, Shin as modified above discloses (See, for example, Fig. 7, Kim’397) that wherein the electrostatic prevention circuit (See, Pars [10012]-[0113]) is operated when static electricity is introduced through any one of the plurality of data input lines (IL1, IL2) and the first (TD) and second (TG) mode control lines of the third type, and is configured to discharge static electricity through an electrostatic discharge line (See, for example, Pars [0112]-[0113]) . . 07-21-aia AIA Claim s 17, 20 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Shin in view of Kawano as applied to claim 1 above; and further in view of Cok et al. (USPN 6747618, hereinafter “Cok”) . In regards to claim 17, Shin as modified above discloses (See, for example, Figs. 2A and 4-7) that wherein the plurality of subpixels include a first color subpixel (red, R) , a second color subpixel (green, G) , and a third color subpixel (blue, B). Shin fails to explicitly teach that a size of the first lens in the first lens region in each of the first, second, and third color subpixels is different from each other, and the number of second lenses in the second lens region in each of the first, second, and third color subpixels is different from each other. Cok while disclosing a display teaches a size of the first lens in the first lens region in each of the first, second, and third color subpixels is different from each other, and the number of second lenses in the second lens region in each of the first, second, and third color subpixels is different from each other ( an OLED color display device in which a display pixel has a plurality of subpixels of different colors, wherein the areas of the subpixels are different in size based on the emission efficiency of the emissive elements and the chromaticity of a target display white point, thereby protecting the subpixels whose emission efficiency is low from prematurely deteriorating, with the relative sizes of the subpixels being further based on the relative luminance stability over time of the subpixels, thereby further extending the useful lifetime of the display (See Claim 1); and the area of the blue subpixels is substantially larger than the area of the red and green subpixels to compensate for the relatively short lifetime of the blue subpixels (See claim 6)). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to modify the display panel of shin as modified above further by Cok because this would help compensate for differences in emission efficiency and luminance stability among the different color OLED materials, thereby protecting subpixels with low emission efficiency from prematurely deteriorating and extending the useful lifetime of the display. In regards to claim 20, Shin as modified above discloses (See, for example, Figs. 24 and 4-7) that wherein the first color subpixel, the second color subpixel, and the third color subpixel are a red subpixel (red, R) , a green subpixel (green, G) and a blue subpixel (blue, B) respectively, wherein a number of the second lenses disposed in the second lens region of the blue subpixel is greater than a number of the second lenses disposed in the second lens region of the red subpixel, and is greater than a number of the second lenses disposed in the second lens region of the green subpixel ( the area of the blue subpixels is substantially larger than the area of the red and green subpixels to compensate for the relatively short lifetime of the blue subpixels (See claim 6)) , and wherein a number of the second lenses (6 second lenses Lz2, Par [0100], Shin) disposed in the second lens region of the green subpixel area (2SP2, Shin) is greater than a number of the second lenses (3 second lenses Lz2, See Par [0100], Shin) disposed in the second lens region of the red subpixel (2SP1, Shin) . In regards to claim 21, Shin as modified above discloses (See, for example, Figs. 2A, 4-7) wherein the first color subpixel, the second color subpixel, and the third color subpixel are a red subpixel (red, R) , a green subpixel (green, G) and a blue subpixel (blue, B) respectively, wherein a size of the first lenses disposed in the first lens region (Lz1) of the blue (B) subpixel is greater than a size of the first lenses disposed in the first lens region of the red (R ) subpixel, and is greater than a size of the first lenses disposed in the first lens region of the green subpixel (G ) , and wherein a size of the first lenses disposed in the first lens region of the green subpixel area is greater than a size of the first lenses disposed in the first lens region of the red subpixel (the lens size varies based on the numbers of sub-sub-pixels and corresponding different lens configurations/size, See Par [0111]) . Allowable Subject Matter 12-151-08 AIA 07-43 12-51-08 Claim s 10, 13 and 23 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Correspondence Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERMIAS T WOLDEGEORGIS whose telephone number is (571)270-5350. The examiner can normally be reached on Monday-Friday 8 am - 5 pm E.S.T.. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached on 571-270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ERMIAS T WOLDEGEORGIS/Primary Examiner, Art Unit 2893 Application/Control Number: 18/427,328 Page 2 Art Unit: 2893 Application/Control Number: 18/427,328 Page 3 Art Unit: 2893 Application/Control Number: 18/427,328 Page 4 Art Unit: 2893 Application/Control Number: 18/427,328 Page 5 Art Unit: 2893 Application/Control Number: 18/427,328 Page 6 Art Unit: 2893 Application/Control Number: 18/427,328 Page 7 Art Unit: 2893 Application/Control Number: 18/427,328 Page 8 Art Unit: 2893 Application/Control Number: 18/427,328 Page 9 Art Unit: 2893 Application/Control Number: 18/427,328 Page 10 Art Unit: 2893 Application/Control Number: 18/427,328 Page 11 Art Unit: 2893 Application/Control Number: 18/427,328 Page 12 Art Unit: 2893 Application/Control Number: 18/427,328 Page 13 Art Unit: 2893 Application/Control Number: 18/427,328 Page 15 Art Unit: 2893 Application/Control Number: 18/427,328 Page 16 Art Unit: 2893 Application/Control Number: 18/427,328 Page 17 Art Unit: 2893
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