Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is a Final office action based on application 18/427,470 in response to reply filed July 2, 2026. Claims 1 & 3-19 are currently pending and have been considered below.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3-4, 6-16, 18-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kang (Pre-Grant Publication 2022/0352061) in view of Tsai (Pre-Grant Publication 2020/0105544).
Regarding claim 1, Kang discloses a semiconductor package comprising:
a first redistribution structure (Fig. 2, 220) comprising a conductive layers/patterns (221);
a second redistribution structure (210) on the first redistribution structure;
a plurality of semiconductor chips (310/320) on an upper surface of the second redistribution structure;
a bridge chip (330) on a lower surface of the second redistribution structure; and
a first molding layer (260) between the first redistribution structure and the second redistribution structure and adjacent to the bridge chip, wherein the first molding layer is between the bridge chip and the first redistribution structure (Fig. 2).
a plurality of conductive posts (265) in the first molding layer and spaced apart from the bridge chip in a horizontal direction.
An upper surface of the conductive layer (221) contacts a conductive post of the plurality of conductive post.
Kang does not disclose a horizontal width of the upper surface of the conductive layer is greater than a horizontal width of the conductive post. However, Tsai discloses a package device comprising:
A first redistribution layer (Fig. 47, 306) having conductive layer (Fig. 33, 322) having width W6 and a conductive post (Fig. 34, 322p) having a width W8 contacting the conductive layer wherein a horizontal width of the upper surface of the conductive layer is greater than a horizontal width of the conductive post.
It would have been obvious to those having ordinary skill in the art at the time of invention to form the conductive layer of the redistribution layer having a greater width than the width of the conductive post because it will reduce a possibly of a misalignment when the conductive post is coupled to the conductive layer/redistribution layer.
Regarding claim 3, Kang further discloses:
a second molding layer (460) on the second redistribution structure and adjacent to the plurality of semiconductor chips.
Regarding claim 4, Kang further discloses:
a height of the first molding layer (260) is different from a height of the second molding layer (460) in a vertical direction (Fig. 2).
Regarding claim 6, Kang further discloses:
a connection member (350) between the bridge chip and the second redistribution structure, wherein the connection member directly contacts the first molding layer (Fig. 2).
Regarding claim 7, Kang further discloses:
the bridge chip is electrically connected to the first redistribution structure through the second redistribution structure (Fig. 2).
Regarding claim 8, Kang further discloses:
the bridge chip overlaps at least two of the plurality of semiconductor chips in a vertical direction (Fig. 2).
Regarding claim 9, Kang further a semiconductor package comprising:
a first redistribution structure (220) comprising a conductive layers/patterns (221);
a second redistribution structure (210) on the first redistribution structure;
a plurality of semiconductor chips (310/320) on an upper surface of the second redistribution structure;
a bridge chip (330) on a lower surface of the second redistribution structure;
a passive device (340) spaced apart from the bridge chip in a horizontal direction and on the lower surface of the second redistribution structure;
a first molding layer (260) between the first redistribution structure and the second redistribution structure and adjacent to the bridge chip and the passive device;
a plurality of conductive posts (265) arranged in the first molding layer and spaced apart from the bridge chip and the passive device in the horizontal direction; and
a second molding layer (460) on the upper surface of the second redistribution structure and adjacent to the plurality of semiconductor chips,
wherein the first molding layer is between the bridge chip and the first redistribution structure and between the passive device and the first redistribution structure (Fig. 2).
An upper surface of the conductive layer (221) contacts a conductive post of the plurality of conductive post.
Kang does not disclose a horizontal width of the upper surface of the conductive layer is greater than a horizontal width of the conductive post. However, Tsai discloses a package device comprising:
A first redistribution layer (Fig. 47, 306) having conductive layer (Fig. 33, 322) having width W6 and a conductive post (Fig. 34, 322p) having a width W8 contacting the conductive layer wherein a horizontal width of the upper surface of the conductive layer is greater than a horizontal width of the conductive post.
It would have been obvious to those having ordinary skill in the art at the time of invention to form the conductive layer of the redistribution layer having a greater width than the width of the conductive post because it will reduce a possibly of a misalignment when the conductive post is coupled to the conductive layer/redistribution layer.
Regarding claim 10, Kang further discloses:
a chiplet/another chip (340) on the lower surface of the second redistribution structure and spaced apart from the bridge chip and the passive device in the horizontal direction.
Regarding claim 11, Kang further discloses:
the chiplet is spaced apart from the first redistribution structure in a vertical direction perpendicular to the horizontal direction (Fig. 2)
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kang (Pre-Grant Publication 2022/0352061).
Regarding claim 12, Kang further discloses:
A height of the passive device (340) is different from a height of the bridge chip (330) in a vertical direction (Fig. 2 & 3).
` Although Kang does not disclose the height of the passive device and the chiplet/another passive device are different from each other it would have been obvious to those having ordinary skill in the art to form multiple chips in the semiconductor package to provide a function to support the operation main semiconductor chips wherein depending on the function the size of the chips may have differing thickness/heights.
Regarding claim 13, Kang further discloses:
The first redistribution structure includes a passivation layer (225);
An underbump metallurgy layer (221) on a portion of a lower surface of the passivation layer.
A conductive layer (221) in contact with the UBM layer.
Kang does not disclose explicitly disclose a conductive layer in contact with the UBM layer and exposed to an upper surface opposite to the lower surface of the passivation layer. However, Tsai discloses a package device comprising:
A redistribution layer (Fig. 32, 306) including a under bump metallurgy (310) on a portion of a passivation layer (308) and a conductive layer (Fig. 32, 322) exposed to an upper surface opposite to the lower surface of the passivation layer.
Tsai further disclose the redistribution layer (306) can be formed with more or fewer dielectric layer and metallization patterns (Paragraph [0070]) therefore the redistribution layer can be formed with the conductive layer (322) in contact with the underbump metallurgy layer (310).
It would have been obvious to those having ordinary skill in the art at the time of invention to form the conductive layer in contact with the UBM because it will minimizing the thickness of the RDL and will minimize manufacturing steps/processes of the RDL.
Regarding claim 14, Kang further discloses:
a height of the first molding layer (260) is lower than a height of the second molding layer (460) in a vertical direction.
Regarding claim 15, Kang further discloses:
a height of the passive device (340) is different from a height of the bridge chip (330) in a vertical direction (Fig. 2 & 3).
Regarding claim 16, Kang discloses a semiconductor package comprising:
The first redistribution structure (Fig. 2, 220) includes a passivation layer (225);
An underbump metallurgy layer (221) on a portion of a lower surface of the passivation layer.
A conductive layer (221) in contact with the UBM layer.
a second redistribution structure (210) comprising at least one redistribution insulating layer (215), a plurality of conductive line patterns (211W) in the at least one redistribution insulating layer and extending in a horizontal direction, and a plurality of conductive vias (211V) in the at least one redistribution insulating layer and extending in a vertical direction perpendicular to the horizontal direction;
a plurality of semiconductor chips (310/320) on an upper surface of the second redistribution structure;
a bridge chip (330) on a lower surface of the second redistribution structure and electrically connecting at least two of the plurality of semiconductor chips;
a passive device (340) on the lower surface of the second redistribution structure and spaced apart from the bridge chip in the horizontal direction;
a first molding layer (260) between the first redistribution structure and the second redistribution structure and adjacent to a side surface of the bridge chip and a side surface of the passive device;
a plurality of conductive posts (265) in the first molding layer and spaced apart from the bridge chip and the passive device in the horizontal direction; and
a second molding layer (460) on the upper surface of the second redistribution structure and adjacent to the plurality of semiconductor chips,
wherein the first molding layer is between the bridge chip and the first redistribution structure and between the passive device and the first redistribution structure (Fig. 2).
An upper surface of the conductive layer (221) contacts a conductive post of the plurality of conductive post.
Kang does not disclose explicitly disclose a conductive layer with the UBM layer and exposed to an upper surface opposite to the lower surface of the passivation layer or a horizontal width of the upper surface of the conductive layer is greater than a horizontal width of the conductive post. However, Tsai discloses a package device comprising:
A first redistribution layer (Fig. 47, 306) having conductive layer (Fig. 33, 322) having width W6 and a conductive post (Fig. 34, 322p) having a width W8 contacting the conductive layer wherein a horizontal width of the upper surface of the conductive layer is greater than a horizontal width of the conductive post.
the redistribution layer including a under bump metallurgy (310) on a portion of a passivation layer (308) and the conductive layer (322) exposed to an upper surface opposite to the lower surface of the passivation layer.
Tsai further disclose the redistribution layer (306) can be formed with more or fewer dielectric layer and metallization patterns (Paragraph [0070]) therefore the redistribution layer can be formed with the conductive layer (322) in contact with the underbump metallurgy layer (310).
It would have been obvious to those having ordinary skill in the art at the time of invention to form the conductive layer of the redistribution layer having a greater width than the width of the conductive post because it will reduce a possibly of a misalignment when the conductive post is coupled to the conductive layer/redistribution layer. Further it would have been obvious to those having ordinary skill in the art at the time of invention to form the conductive layer in contact with the UBM because it will minimizing the thickness of the RDL and will minimize manufacturing steps/processes of the RDL.
Regarding claim 18, Kang further discloses:
a passive device connection member (350) between the passive device and the second redistribution structure; and a bridge chip connection member (350) between the bridge chip and the second redistribution structure, wherein each of the passive device connection member and the bridge chip connection member comprises at least one of a solder ball and a conductive pillar (Fig. 3).
Regarding claim 19, Kang further discloses:
an upper surface of the second molding layer and upper surfaces of the plurality of semiconductor chips are coplanar (Fig. 2).
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kang (Pre-Grant Publication 2022/0352061) in view of Tsai (Pre-Grant Publication 2020/0105544) as applied to claim 1 above, and further in view of Duan (Pre-Grant Publication 2025/0105209).
Regarding claim 5, Kang and Tsai disclose all of the limitations of claim 1 (addressed above). Kang further discloses:
a connection member (350) between the bridge chip and the second redistribution structure.
Kang does not explicitly disclose an underfill layer adjacent to the connection member. However Duan disclose a semiconductor package comprising:
A bridge chip (Fig. 1, 114-1B) having a connection member (132) wherein an underfill (127-1) is adjacent the connection member.
It would have been obvious to those having ordinary skill in the art at the time of invention to form the underfill adjacent to the connection member of the bridge chip because it will serve to support the chip and reduce thermal stress on interconnects (Paragraph [0041]).
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kang (Pre-Grant Publication 2022/0352061) in view of Tsai (Pre-Grant Publication 2020/0105544) as applied to claim 16 above, and further in view of Chen (Pre-Grant Publication 2025/0132296).
Regarding claim 17, Kang and Tsai discloses all of the limitations of claim 16 (addressed above). Neither reference disclose each of the conductive vias has a tapered shape with a horizontal width decreasing away from the semiconductor chips. However Chen discloses a semiconductor package comprising:
A second redistribution layer (Fig. 2h, 260) having conductive vias (162v; Paragraph [0031]) that have a tapered shape wherein a horizontal width decreases away from a plurality of semiconductor chips (170a-170c).
It would have been obvious to those having ordinary skill in the art at the time of invention to form the conductive vias of Kang having a tapered shape wherein a horizontal width decrease away from the semiconductor chips as disclose by Chen since it has been held that the tapered shape of the conductive vias away from the semiconductor chips can be a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed shape was significant. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966) MPEP 2144.04 IV B
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 9 & 16 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRANDON C FOX whose telephone number is (571)270-5016. The examiner can normally be reached M-F 9:00AM-6:00PM.
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/BRANDON C FOX/Examiner, Art Unit 2818
/DAVID VU/Primary Examiner, Art Unit 2818
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