Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Response, received 9/15/2026, has been entered.
Claims 1-20 are presented for examination.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 4-7 and 10-12 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Muroga (US Pub. No. 2022/0130746 A1).
As to claim 1, Muroga discloses a semiconductor package (fig 2) comprising:
a semiconductor chip (81); and
a package substrate (10) comprising:
a base layer (20);
a plurality of upper bump pads (31) disposed on the base layer (20);
an upper passivation layer (40) disposed on the base layer (20), the upper passivation layer comprising a plurality of first openings (41); and
an insulating patch (60; [0018]) disposed between an outer region of the semiconductor chip (81) and the upper passivation layer (40), the insulating patch comprising a plurality of patch openings (openings in 60); and
a plurality of bump structures (70) disposed between the plurality of upper bump pads (31) and the semiconductor chip (81),
wherein each of the plurality of bump structures (70) is disposed on a corresponding one of the plurality of upper bump pads (31) through a corresponding one of the plurality of first openings (41) of the upper passivation layer (40) and a corresponding one of the plurality of patch openings (openings of 60) of the insulating patch (60).
As to claim 4, Muroga discloses the semiconductor package of claim 1 (paragraphs above),
wherein a material of the insulating patch is different from a material of the upper passivation layer ([0030]).
As to claim 5, Muroga discloses the semiconductor package of claim 1 (paragraphs above),
wherein a coefficient of thermal expansion of the insulating patch is different from a CTE of the upper passivation layer ([0030]).
As to claim 6, Muroga discloses the semiconductor package of claim 1 (paragraphs above),
wherein the insulating patch (60) vertically overlaps a corner region of the semiconductor chip (81).
As to claim 7, Muroga discloses the semiconductor package of claim 6 (paragraphs above),
wherein the insulating patch (60) comprises an overlap region vertically overlapping the corner region of the semiconductor chip (81) and a non-overlap region (region of 60 outside and not overlapping chip 81) that does not vertically overlap the semiconductor chip (81), and
the plurality of patch openings are in the overlap region of the insulating patch (openings in 60 overlapping with chip 81).
As to claim 10, Muroga discloses the semiconductor package of claim 1 (paragraphs above),
wherein the package substrate further comprises a dam (portion of 60 at edge of underfill 85) structure disposed on the upper passivation layer (40), the dam structure (structure of 60) at least partially surrounding the semiconductor chip (81).
As to claim 11, Muroga discloses the semiconductor package of claim 10 (paragraphs above),
wherein a material of the dam structure and a material of the insulating patch are same as each other ([0018]).
As to claim 12, Muroga discloses the semiconductor package of claim 10 (paragraphs above),
wherein the dam structure is connected to the insulating patch (structure of 60 surrounding at edge of underfill 85 is connected to 60), and
a top surface of the dam structure is coplanar with a top surface of the insulating patch (top surface of 60 is coplanar).
Claim(s) 1-3 and 8-9 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tsai et al. (US Pub. No. 2008/0277802 A1), hereafter referred to as Tsai.
As to claim 1, Tsai discloses a semiconductor package (fig 7) comprising:
a semiconductor chip (50); and
a package substrate (4) comprising:
a base layer (40);
a plurality of upper bump pads (41) disposed on the base layer (40);
an upper passivation layer (43) disposed on the base layer (40), the upper passivation layer comprising a plurality of first openings (openings in 43); and
an insulating patch (42) disposed between an outer region of the semiconductor chip (50) and the upper passivation layer (43), the insulating patch comprising a plurality of patch openings (openings in 42); and
a plurality of bump structures (51) disposed between the plurality of upper bump pads (41) and the semiconductor chip (50),
wherein each of the plurality of bump structures (51) is disposed on a corresponding one of the plurality of upper bump pads (41) through a corresponding one of the plurality of first openings of the upper passivation layer (openings in 43) and a corresponding one of the plurality of patch openings of the insulating patch (openings in 42).
As to claim 2, Tsai discloses the semiconductor package of claim 1 (paragraphs above),
wherein a material of the insulating patch is same as a material of the upper passivation layer ([0036]).
As to claim 3, Tsai discloses the semiconductor package of claim 1 (paragraphs above),
wherein a material of the insulating patch and a material of the upper passivation layer each comprise a solder resist ([0036]).
As to claim 8, Tsai discloses the semiconductor package of claim 1 (paragraphs above),
wherein the upper passivation layer exposes a center region of the base layer (opening in 42 exposing base layer 40), and the center region is at least partially surrounded by an outer region covered by the upper passivation layer (outer region covered by 43).
As to claim 9, Tsai discloses the semiconductor package of claim 8 (paragraphs above),
an underfill material layer (52) disposed in a gap between the semiconductor chip (50) and the package substrate (4),
wherein the underfill material layer (52) is in contact with the insulating patch (42), the plurality of bump structure (41), and the center region of the base layer (40).
Claim(s) 18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al. (US Pub. No. 2022/0181309 A1), hereafter referred to as Lee.
As to claim 18, Lee discloses a package substrate (fig 2A) comprising:
a base layer (111);
a plurality of upper bump pads (141) disposed on the base layer (111);
an upper passivation layer (113) disposed on the base layer (111), the upper passivation layer comprising a through hole exposing a center region of the base layer (hole in 113 exposing center of 111) and a plurality of first openings exposing the plurality of upper bump pads (openings in 113 exposing 141); and
a plurality of insulating patches (150 on left side and 150 on right side, see fig 3A) on the upper passivation layer (113), the plurality of insulating patches being disposed apart from each other (fig 3A, 150 on left apart from 150 on the right),
wherein each of the plurality of insulating patches (150) comprises a plurality of patch openings (openings in 150 for solder 145), aligned with the plurality of first openings of the upper passivation layer (openings in 150 for conductor 145 are aligned with openings in 113 for conductor 141).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 13 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Muroga in view of Lee (US Pub. No. 2021/0391277 A1), hereafter referred to as Lee2.
As to claim 13, Muroga discloses the semiconductor package of claim 10 (paragraphs above).
Muroga does not disclose wherein the dam structure is disposed apart from the insulating patch.
Nonetheless, Lee2 discloses wherein a dam structure is disposed apart from the underfill region (fig 2, dam 208).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to include the dam structure of Lee2 in the semiconductor package of Muroga since this will improve the outflow control of the underfill material.
As to claim 14, Muroga discloses the semiconductor package of claim 1 (paragraphs above).
Muroga further discloses wherein each of the plurality of bump structures comprises:
a solder layer (83; [0057]) between the chip (81) and a corresponding one of the plurality of upper bump pads (31),
wherein the solder layer (83) is in contact with a sidewall of the insulating patch (60), and
wherein the sidewall of the insulating patch defines a corresponding one of the plurality of patch openings of the insulating patch (opening in 60).
Muroga does not disclose wherein a conductive pillar disposed on the semiconductor chip; and a solder layer between the conductive pillar and a corresponding one of the plurality of upper bump pads.
Nonetheless, Lee2 discloses wherein each of the plurality of bump structures (fig 6, bump structure between chip 602 and substrate 401) comprises:
a conductive pillar disposed on the semiconductor chip (pillar shown on chip 602; [0021]); and
a solder layer between the conductive pillar and a corresponding one of the plurality of upper bump pads (fig 6, solder layer between pillar on chip 602 and one of pads 403; [0021]).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to include the conductive pillar on the semiconductor chip with the solder in contact with the bump pad in the semiconductor package of Muroga as taught in Lee2 since this will improve the standoff height of the semiconductor chip with the package substrate.
Allowable Subject Matter
Claims 15-17 are allowed.
Claims 19-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The prior art of record fails to teach or suggest all of the limitations of claim 15, specifically, a distance between at least one of the plurality of second solder layers and the base layer is greater than a distance between at least one of the plurality of first solder layers and the base layer. Claims 16-17 are allowable because of their dependence from claim 15. The prior art of record fails to teach or suggest all of the limitations of claim 19, specifically, wherein the upper passivation layer, the plurality of insulating patches, and the dam structure comprise a same material as each other. Claim 20 is objected to as being allowable because of its dependence from claim 19.
Response to Arguments
Applicant's arguments filed 9/15/2026 have been fully considered but they are not persuasive.
Applicant argued that the element labels used in the Office Action do not replace the required structure. A continuous substrate layer, a flow control protrusion, or portions of a later applied gap filler are not the claimed insulating patch merely because they occupy space near a semiconductor chip.
Examiner disagrees because the element labels used in the Office Action do meet the limitations as recited in the claims, as detailed above. The claim limitations are not met merely because they occupy space but instead because they meet the limitations according to BRI.
Applicant argued that Muroga does not disclose a bump structure disposed on pad 31 through one corresponding opening of layer 40 and one corresponding opening of a separate insulating patch in the arrangement required by claim 1.
Examiner disagrees because Muroga does disclose bump structure 70 disposed on upper bump pad 31 through first opening 41 of the upper passivation layer 40 and a corresponding one of openings in patch 60.
Applicant argued that layer 60 does not have the plan view form now recited in claim 1.
Examiner disagrees because the cross sectional view shown in figure 2 does disclose a cross-sectional arrangement of the planar view. Additionally, claim 1 does not recite limitations with regard to planar view.
Applicant argued that Muroga does not anticipate claim 1 because Muroga fails to disclose: layer 60 covering at least one first edge portion of layer 40 while exposing an intervening second edge portion, and does not describe the semiconductor chip overlapping upper surfaces of each first edge portion. Nor does Muroga describe a localized patch between a lower surface of an outer chip region and an upper surface of a passivation layer in combination with those plan view relationships. Muroga therefore does not anticipate claim 1. The passages relied on for material composition and coefficient of thermal expansion do not cure the missing claim 1 architecture, so claims 4 and 5 remain patentable. A continuous layer also does not provide the corner overlap, the separate region that does not vertically overlap the chip, and the placement of patch openings in the overlap region required by claims 6 and 7. For claims 10 through 12, the Office Action identifies a portion of layer 60 at the edge of underfill resin 85 as a dam. That portion is not a distinct dam structure disposed on the upper passivation layer and at least partially surrounding the semiconductor chip. Muroga therefore does not describe the separate patch and dam structures required by claim 10, the same material relationship of claim 11, or the connected and coplanar relationships of claim 12.
Examiner disagrees because these arguments do not correspond to the limitations required by the claims.
Applicant argued that the Tsai reference does not cure the deficiencies of Muroga with respect to claim 1.
Examiner disagrees because Muroga anticipates all of the limitations of claim 1.
Applicant argued that Lee does not anticipate claim 18 because Lee fails to disclose the claimed dam structure.
Examiner disagrees because claim 18 does not require a dam structure.
Applicant argued that the obvious type rejections of claims 13-14 cannot be established because the limitations of the independent claim 1 are not met.
Examiner disagrees because the limitations of claim 1 are anticipated.
Applicant argued that it would not have been obvious to one of ordinary skill in the art to combine Muroga in view of Lee with regard to claim 13.
Examiner disagrees because it would have been obvious to include the dam structure of Lee in the semiconductor package of Muroga since this will improve the outflow control of the underfill material.
Applicant argued that it would not have been obvious to one of ordinary skill in the art to combine the device of Muroga in view of the teaching of Lee with respect to claim 14 because neither Muroga nor Lee provides a design basis for the coordinated changes of: opening geometry, pillar position and height, solder volume, wetting surfaces, reflow behavior, materials, and electrical isolation.
Examiner disagrees because determining the exact modifications of positions, height, volume wetting surfaces, reflow behavior, materials, electrical shorting are all performed according to routine experimentation that one of ordinary skill in the art performs during the manufacture for all semiconductor devices.
Pertinent Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US 9,549,472B2 and
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAUN M CAMPBELL whose telephone number is (571)270-3830. The examiner can normally be reached on MWFS: 7:30-6pm Thurs 1-2pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Purvis, Sue can be reached at (571)272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHAUN M CAMPBELL/Primary Examiner, Art Unit 2893
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