DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention II, Species (Figs. 2A-2D) covered by claims 1-8 in the reply filed on July 1, 2026 is acknowledged. Claim 9-20
withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention and species, there being no allowable generic or linking claim. Accordingly, claim1-8 are ready for examination.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3 and 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Iwaki (US 2021/0050352, hereinafter “Iwaki”) in view of Pawlak et al. (US 2008/0057685, hereinafter “Pawlak”) and Hu (US 6,365,507, hereinafter “Hu”) or Oh (US 2008/0111201, hereinafter “Oh”).
Regarding claim 1, Iwaki teaches in Figs. 1A-13B (Figs. 1A-1B shown below) and related text a method of forming an apparatus, the method comprising:
forming a crystalline semiconductor material comprising one or more of a monocrystalline material (165, Figs. 1A-1B) and a nanocrystalline material adjacent to active areas of memory cells (105, Figs. 1A-1B);
forming a metal material (¶[0044]);
converting the metal material to form a metal silicide material adjacent to the crystalline semiconductor material (¶[0044]);
forming cell contacts (180, Fig. 1B) over the metal silicide material (170, Figs. 1A-1B); and
forming a storage node (¶¶[0046] and [0049]) adjacent to the cell contacts (Figs. 1A-1B and ¶[0046]).
PNG
media_image1.png
313
519
media_image1.png
Greyscale
Iwaki, however, does not explicitly teach that an amorphous material is formed within portions of the crystalline semiconductor material, and as a result, that a portion of the amorphous material and the metal material are converted to form a metal silicide material adjacent to the crystalline semiconductor material and that forming a metal material comprising forming a metal material comprising one or more of chlorine atoms and nitrogen atoms over the amorphous material.
To begin with Pawlak, in a similar field of endeavor teaches in Figs. 1-4 amorphizing a crystalline silicon region (2, Fig. 1 and ¶[0084]) prior to forming a metal layer (12, Fig. 2 and ¶[0091]) thereon and converting the amorphous material and the metal material to form a metal silicide material (14, Fig. 3 and ¶[0092]) adjacent to a crystalline semiconductor materials (10, Fig. 2 and [0088]) in order to increase silicide formation process and improve the interface between silicide layer and the crystalline semiconductor (¶[0090]), whereas Hu or Oh teach that the silicide-forming metal, such as titanium (Ti), may include nitrogen (Hu, col. 2, ll. 22-27 and col. 4, ll. 1-57 and Oh, ¶[0018]) in order to improve formation of metal silicide region (Hu, col. 2, ll. 1-17 and col. 5, ll. 25-48).
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the invention pertains to amorphized crystalline silicon disclosed by Iwaki, so that an amorphous material is formed within the crystalline semiconductor material, and to form a metal material comprising nitrogen over the amorphous material, so that the amorphous material and the metal material are converted to a metal silicide material as disclosed by Pawlak and Hu or Oh in order to increase and improve silicide formation process.
Regarding claim 2 (1), the combined teaching of Iwaki, Pawlak, Hu or Oh discloses wherein forming the metal material and converting the portion of the amorphous material and the metal material comprises depositing a metal comprising titanium using a CVD process (Iwaki, ¶[0012]) and annealing the metal to form the metal silicide material (Iwaki, ¶[0044], Pawlak, ¶[0092]).
Regarding claim 3 (1), the combined teaching of Iwaki, Pawlak, Hu or Oh further discloses forming the metal material (Iwaki, ¶[0044] and Pawlak, 12, Fig. 2 and ¶[0091]) over the amorphous material (Pawlak, 7, Fig. 2 and ¶[0087]) and forming a metal contact material (Iwaki, 260 (180), Figs. 1A-1B, 12B and ¶¶[0028] and [0045]-[0046]) of the cell contacts in a single, substantially continuous process, without forming a nitride barrier material over the metal silicide material (Iwaki, Figs. 1A-1B and 12B).
Regarding claim 5 (1), the combined teaching of Iwaki, Pawlak and Hu or Oh discloses wherein forming the amorphous material comprises substantially converting a phosphorus-doped crystalline silicon material (Iwaki, ¶[0040]) using a pre-amorphization implant process to form a phosphorus-doped amorphous silicon material (i.e. Iwaki teaches that phosphorus is implanted into the monocrystalline silicon material 165, ¶[0040], prior to amorphization process disclosed by Pawlak, ¶[0084]).
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Iwaki, Pawlak and Hu or Oh as applied to claim 1 above, and further in view of in view of Araki (US 2006/0194419, hereinafter “Araki”) or Yamazaki et al. (US 5,840,600, hereinafter “Yamazaki”).
Regarding claim 4 (1), the combined teaching of Iwaki, Pawlak and Hu or Oh was discussed above in the reject on of claim 1. Iwaki, Pawlak and Hu or Oh, however, do not explicitly teach wherein forming the crystalline semiconductor material comprises forming an amorphous silicon material adjacent to the active areas of the memory cells, and conducting a laser anneal act to convert the amorphous silicon material to the crystalline semiconductor material. Nonetheless, forming crystalline semiconductor material by laser annealing an amorphous silicon material, is well-known in the art, as evidenced by Araki (¶[0008]-[0011]) or Yamazaki (col. 5, ll. 38-44).
Thus, since the prior art teaches all of the method steps, using such steps would lead to predictable results, and as such, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form crystalline semiconductor material disclosed by Iwaki, Pawlak and Hu or Oh by laser annealing as doing so would amount to nothing more than using a known method for its intended purpose.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Iwaki, Pawlak and Hu or Oh, as applied to claim 5 above, and further in view of Araki (US 2006/0194419, hereinafter “Araki”) or Saarela et al. (US 2024/0339985, hereinafter “Saarela”).
Regarding claim 6 (5), the combined teaching of Iwaki, Pawlak and Hu or Oh was discussed above and includes doping phosphorus into crystalline silicon material (Iwaki, ¶[0040]) prior to the amorphization of the phosphorus-doped crystalline silicon.
Iwaki, Pawlak and Hu or Oh, however, do not explicitly teach exposing the phosphorus-doped crystalline silicon material to annealing conditions to diffuse one or more dopants from upper portions of the crystalline semiconductor material into lower portions thereof after performing the pre-amorphization implant process (i.e. after implanting phosphorus) and prior to forming the metal silicide material.
Araki or Saarela, in a similar field of endeavor, teaches that a phosphorus-doped crystalline silicon might be exposed to annealing conditions (i.e. heat, Araki, ¶¶[0039]-[0040] and Saarela, ¶[0089]) in order to drive dopants to a desired depth within the crystalline semiconductor material.
Accordingly, since the prior art teaches all of the steps of the claim, using such steps would lead to predictable results, and as such, it would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to expose the phosphorus-doped crystalline silicon material to annealing conditions as disclosed by Araki and Saarela, after performing the pre-amorphization implant process, in order to drive dopants to a desired depth within the crystalline semiconductor material.
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Iwaki, Pawlak and Hu or Oh as applied to claim 1 above, and further in view of Araki (US 2006/0194491, hereinafter “Araki”) and Mikhalev et al. (US 8,906,771, hereinafter “Mikhalev”).
Regarding claim 7 (1), the combine teaching of Iwaki, Pawlak and Hu or Oh was discussed above and includes etching crystalline semiconductor material (Iwaki, 165, Figs. 1A-1B and 10A-10B) using dry etching (Iwaki, ¶[0043]) and subjecting the crystalline semiconductor material to an implant process using Ge, Xe, Ar, or He in order to form the amorphous material (Pawlak, ¶[0084]). Iwaki, Pawlak and Hu or Oh, however, do not explicitly teach that hydrogen chloride is formed within upper portions of the crystalline semiconductor material and that amorphous material is formed by subjecting the crystalline semiconductor material to an implant process using one or more of arsenic and antimony.
To begin with, etching crystalline semiconductor material using wet etching with HCl, rather dry etching as disclosed by Iwaki, is well-known in the art as evidenced by Araki (¶[0038]). Specifically, Araki teaches dry etching and wet etching of equivalent process for etching crystalline silicon that can be used depending on specific manufacturing requirements.
Accordingly, because these two processes were art recognized equivalents before the effective filing data of the invention, one of ordinary skill in the art would found it obvious to etch crystalline silicon disclosed by Iwaki, Pawlak and Hu or Oh, using HCl wet etch rather than dry etch. It is noted that according to the Applicant (¶¶[0045]-[0047] and [0058] of the specification as published), etching crystalline semiconductor material with HCl results in the HCl being formed with the upper portions of the crystalline semiconductor.
Additionally, Mikhalev, in a similar field of endeavor, teaches that crystalline semiconductor (silicon) (col. 2, ll. 25-47), disclosed by Iwaki, Pawlak and Hu or Oh, can be amorphized by subjecting the crystalline semiconductor material to an implant process using one or more of arsenic and antimony (col. 5, ll. 34-52).
Accordingly, since the prior art teaches all of the claim elements, using such elements would lead to predictable results, and as such, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to subject the crystalline semiconductor material of Iwaki, Pawlak, Hu or Oh and Araki to an implant process using arsenic in order to form an amorphous material, as disclosed by Mikhalev, as it would amount to nothing more than using an atom that is known for amorphizing crystalline semiconductor material.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Iwaki, Pawlak and Hu or Oh as applied to claim 1 above, and further in view of Walters et al. (US 2022/0102384, hereinafter “Walters”).
Regarding claim 8 (1), the combined teaching of Iwaki, Pawlak and Hu or Oh was discussed above in the rejection of claim 1, and includes forming a crystalline semiconductor material on the active areas of the memory cells, the crystalline material including a monocrystalline material (Iwaki, ¶¶[0009] and [0028]). Iwaki, Pawlak and Hu or Oh, however, do not explicitly teach that that a nanocrystalline material is formed adjacent to the monocrystalline material in a single, substantially continuous process.
Walters, in a similar field of endeavor, teaches that crystalline silicon can be grown epitaxially using dichlorosilane (DCS) (¶[0027], which according to the Applicant, results in both monocrystalline and nanocrystalline forms of silicon to be formed in a single, substantially continuous process (¶[0038] of the specification as published)), in order to meet specific manufacturing requirements for the device.
Thus, since the prior art teaches all of the method steps, using such steps would lead to predictable results, and as such, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to epitaxially grow the crystalline semiconductor material disclosed by Iwaki, Pawlak and Hu or Oh, using DCS disclosed by Walters, in order to form a crystalline semiconductor material that comprises both monocrystalline and nanocrystalline material adjacent to the monocrystalline material, in a single, substantially continuous process, in order to meet specific manufacturing reequipments for the device.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANETA B CIESLEWICZ whose telephone number is 303-297-4232. The examiner can normally be reached M-F 8:30 AM - 2:30 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached at 571-272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/A.B.C/Examiner, Art Unit 2893
/SUE A PURVIS/Supervisory Patent Examiner, Art Unit 2893
Prosecution Insights