DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-7 and 10-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20160379871 (Tsai et al) in view of US 20200105591 (Lin et al).
Concerning claim 1, Tsai discloses a semiconductor device comprising (Figs. 1B and 4-9): a first interlayer insulating layer (104) disposed on a substrate (102); a first conductive line (106A and 106B) disposed in the first interlayer insulating layer and having a protrusion protruding above an upper side of the first interlayer insulating layer (Fig. 1B and [0016]); an etch stop layer (108 and 110) disposed on the first interlayer insulating layer and the first conductive line ([0017]); and a via (112A) passing through the etch stop layer and contacting the first conductive line (Fig. 1B), wherein the etch stop layer includes a first etch stop layer (108) having a curved shape in a cross-sectional view and a second etch stop layer (110) disposed on the first etch stop layer and having a thickness variation (Fig. 1B and [0030]).
Tsai does not disclose the first etch stop layer is uneven on the upper side of the first conductive line. However, Lin discloses a semiconductor structure that forms a contact/via structures that are shrunk for high-density gate pitch requirement to address bridging, high contact resistance, patterning issues, and manufacturing cost for enhanced circuit performance and reliability ([0002]). Lin discloses a via passing through the etch stop layer and contacting the first conductive line, wherein the etch stop layer includes a first etch stop layer (218-1) having a curved shape in a cross-sectional view and a second etch stop layer (218-2) disposed on the first etch stop layer and having a thickness variation, and the first etch stop layer is uneven on the upper side of the first conductive line (Figs. 12-13 and [0019]-[0022], it is noted that the etch stop layers are formed of materials with selective depositions and etchings to form self-aligned dielectric structures). It would have been obvious to one of ordinary skill in the art to modify the first and etch stop layers of Tsai in view of the configuration of Lin to have the first etch stop layer uneven on the upper side of the first conductive line in order to address bridging and high contact resistance issues in contact structures.
Continuing to claim 2, Tsai in view of Lin discloses wherein the protrusion of the first conductive line has a height between about 1 to 10 nanometers above the upper side of the first interlayer insulating layer (Tsai [0027]).
Considering claim 3, Tsai in view of Lin discloses wherein a height of the first etch stop layer gradually increases toward a central portion of the first conductive line (Tsai Fig. 6 and [0028] and Lin Fig. 12).
According to claims 4 and 5, Tsai in view of Lin discloses that the first etch stop layer has a radius of curvature
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(Tsai Fig. 6, note that the radius of curvature as seen in annotated Fig. 6 is the thickness of the film which is disclosed to be 1 nm to 7 nm at the upper limit of the thickness range [0028]).
Tsai in view of Lin does not disclose wherein the first etch stop layer has a radius of curvature of about 8 to 48 nanometers or wherein a thickness of the first etch stop layer at an apex is about 0.5 to 4 nanometers from an upper side of the first conductive line. However, a prima facie case of obviousness exists where the claimed ranges or amounts do not overlap with the prior art but are merely close. In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990) (The prior art taught carbon monoxide concentrations of "about 1-5%" while the claim was limited to "more than 5%." The court held that "about 1-5%" allowed for concentrations slightly above 5% thus the ranges overlapped.). See MPEP 2144.05 I. Therefore with the thickness of the layer being slightly below 8 nanometers (7 nanometers) and a range of thickness being 1 nanometer to 7 nanometer there exists a prima facie case of obviousness without evidence of the criticality of the claimed ranges.
Referring to claim 6, Tsai in view of Lin discloses wherein an average thickness of the second etch stop layer is greater than an average thickness of the first etch stop layer (Tsai Fig. 7 and [0030] and Lin Fig. 12, note that the second etch stop layer is shown to have a greater thickness than the first etch stop layer).
Regarding claim 7, Tsai in view of Lin discloses wherein a first portion of the second etch stop layer overlapping the first interlayer insulating layer in a direction that is perpendicular to the substrate is thicker than a second portion of the second etch stop layer overlapping the first conductive line in the direction that is perpendicular to the substrate (Tsai Fig. 7 and Lin Fig. 12).
Pertaining to claim 10, Tsai in view of Lin discloses wherein the via does not pass through a portion of the first etch stop layer overlapping the first interlayer insulating layer in a direction that is perpendicular to the substrate (Tsai Fig. 9 and Lin Fig. 13).
As to claim 11, Tsai in view of Lin discloses wherein the via is disposed above and does not pass through a portion of the first etch stop layer overlapping the first interlayer insulating layer in a direction that is perpendicular to the substrate (Tsai Fig. 9 and Lin Fig. 13).
Concerning claim 12, Tsai discloses a semiconductor device comprising (Figs. 1B, and 4-10): a first interlayer insulating layer (104); a plurality of lower conductive lines (106A and 106B) spaced from each other by the first interlayer insulating layer (Fig. 10); an etch stop layer (108 and 110) disposed on the first interlayer insulating layer and a first lower conductive line of the lower conductive lines (Fig. 10); a second interlayer insulating layer (114) disposed on the etch stop layer (Fig. 10); a via (112A) passing through the second interlayer insulating layer and the etch stop layer and contacting the first lower conductive line (Fig. 10, note that the opening for the via structure passes through the etch stop and the second interlayer insulating layer); and an upper conductive line (116A) disposed on the via, wherein the first lower conductive line has a protrusion protruding above an upper side of the first interlayer insulating layer (Fig. 10), the etch stop layer includes a first etch stop layer (108) in a curved shape in a cross-sectional view and a second etch stop layer (110) disposed on the first etch stop layer and having a thickness variation ([0030]), and a portion of the via is disposed above and does not pass through a portion of the first etch stop layer overlapping the first interlayer insulating layer between the plurality of lower conductive lines (Fig. 10, note that the via is aligned with the top of the conductive line).
Tsai does not disclose the first etch stop layer is uneven on the upper side of the first conductive line. However, Lin discloses a semiconductor structure that forms a contact/via structures that are shrunk for high-density gate pitch requirement to address bridging, high contact resistance, patterning issues, and manufacturing cost for enhanced circuit performance and reliability ([0002]). Lin discloses a via passing through the etch stop layer and contacting the first conductive line, wherein the etch stop layer includes a first etch stop layer (218-1) having a curved shape in a cross-sectional view and a second etch stop layer (218-2) disposed on the first etch stop layer and having a thickness variation, and the first etch stop layer is uneven on the upper side of the first conductive line (Figs. 12-13 and [0019]-[0022], it is noted that the etch stop layers are formed of materials with selective depositions and etchings to form self-aligned dielectric structures). It would have been obvious to one of ordinary skill in the art to modify the first and etch stop layers of Tsai in view of the configuration of Lin to have the first etch stop layer uneven on the upper side of the first conductive line in order to address bridging and high contact resistance issues in contact structures.
Continuing to claim 13, Tsai in view of Lin discloses a method for manufacturing a semiconductor device comprising (Figs. 4-9): forming a first conductive line (106A and 106B) in a first interlayer insulating layer (104) (Fig. 4); recessing the first interlayer insulating layer to form a protrusion of the first conductive line protruding above an upper side of the first interlayer insulating layer (Fig. 5 and [0027]); forming a first etch stop layer (108) in a curved shape to cover the first interlayer insulating layer and the protrusion of the first conductive line (Fig. 6 and [0028]); forming a second etch stop layer (110) with a thickness variation on the first etch stop layer (Fig. 7 and [0029]); and forming a via (Figs 8 and 9) passing through the first etch stop layer and the second etch stop layer (Figs. 8 and 9).
Tsai does not disclose the first etch stop layer is uneven on the upper side of the first conductive line. However, Lin discloses a semiconductor structure that forms a contact/via structures that are shrunk for high-density gate pitch requirement to address bridging, high contact resistance, patterning issues, and manufacturing cost for enhanced circuit performance and reliability ([0002]). Lin discloses a via passing through the etch stop layer and contacting the first conductive line, wherein the etch stop layer includes a first etch stop layer (218-1) having a curved shape in a cross-sectional view and a second etch stop layer (218-2) disposed on the first etch stop layer and having a thickness variation, and the first etch stop layer is uneven on the upper side of the first conductive line (Figs. 12-13 and [0019]-[0022], it is noted that the etch stop layers are formed of materials with selective depositions and etchings to form self-aligned dielectric structures). It would have been obvious to one of ordinary skill in the art to modify the first and etch stop layers of Tsai in view of the configuration of Lin to have the first etch stop layer uneven on the upper side of the first conductive line in order to address bridging and high contact resistance issues in contact structures.
Considering claim 14, Tsai in view of Lin discloses wherein the recessing of the first interlayer insulating layer includes recessing the first interlayer insulating layer by a reactive ion etching process (Tsai [0027]).
Referring to claim 15, Tsai in view of Lin discloses wherein the first etch stop layer is formed by a chemical vapor deposition process, a physical vapor deposition sputtering process, or a selective deposition process (Tsai [0028]).
Regarding claim 16, Tsai in view of Lin discloses further comprising forming a second interlayer insulating layer (Tsai 114) on the second etch stop layer (Tsai Fig. 10).
Pertaining to claim 17, Tsai in view of Lin discloses wherein the forming of the via comprises: etching the second etch stop layer (Tsai Fig. 8 and Lin Fig. 13); and a top corner rounding process for rounding a corner of the second interlayer insulating layer (Tsai Fig. 10, note that the bottom of the upper conductive line has a rounded corner indicating that the opening has rounding at the corner).
As to claim 18, Tsai in view of Lin discloses wherein the forming of the second etch stop layer includes forming a first portion of the second etch stop layer overlapping the first interlayer insulating layer and a second portion of the second etch stop layer overlapping the first conductive line, wherein the first portion is thicker than the second portion (Tsai Fig. 7).
Concerning claim 19, Tsai discloses wherein the forming of the via includes ending a process for etching the second etch stop layer when the second portion of the second etch stop layer overlapping the first conductive line is etched and the first etch stop layer is exposed (Tsai Fig. 10).
Continuing to claim 20, Tsai in view of Lin discloses wherein the forming of the via includes ending a process for etching the second etch stop layer while at least a portion of the first portion of the second etch stop layer overlapping the first interlayer insulating layer and disposed below the via remains when the second portion of the second etch stop layer overlapping the first conductive line is etched and the first etch stop layer is exposed (Tsai Fig. 10).
Claim(s) 8 and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20160379871 (Tsai et al) in view of US 20200105591 (Lin et al) as applied to claim 7 above, and further in view of US 20140312508 (Boyanov et al).
Referring to claims 8 and 9, Tsai in view of Lin discloses forming a first and second portion of the second etch stop (Tsai Fig. 10 and Lin Fig. 12 and [0019], the examiner is relying on the lower end of contact height range (10nm) which would yield the 3 etch stop layers to be around 3.3 nm).
Tsai in view of Lin does not disclose wherein an average thickness of the second portion of the second etch stop layer is about 0.5 to 5 nanometers or wherein an average thickness of the first portion of the second etch stop layer is about 1.5 to 8 nanometers. However, Boyanov discloses an interconnect structure in which a conductive line portions (Metal A, Metal B, and Metal C) are formed in an interlayer insulating layer (ILD) (Fig. 2A) with the ILD being recess below a surface of the conductive line (Fig. 2B), and an etch stop layer (etchstop and OEEL (optional extended etchstop layer) (which is formed a similar material as the second etch stop layer of Tsai ([0023]). Boyanov discloses that the optional extended etchstop layer thickness may vary from one embodiment to the next, and in some embodiments the flowable layer can merely fills the spaces between the metal lines, while in other embodiments it may cover the etchstop above the metal lines with a relatively thin layer (e.g., ranging from a monolayer to 10 nm, or otherwise, so long as a desired etch profile between the off-target landing pad and the target landing pad can be achieved). In some embodiments, the actual layer thickness may vary greatly from one point to the next along the flowable layer, and achieving a perfectly smooth upper surface as shown in FIG. 3A is not necessary. In one specific example, a flowable carbide layer effectively increases the thickness of the conformal etchstop layer above the off-target landing pad, thus improving the ability of the unlanded portion of the via to not penetrate below the conformal etchstop ([0024]). In re Williams, 36 F.2d 436, 438, 4 USPQ 237 (CCPA 1929) ("It is a settled principle of law that a mere carrying forward of an original patented conception involving only change of form, proportions, or degree, or the substitution of equivalents doing the same thing as the original invention, by substantially the same means, is not such an invention as will sustain a patent, even though the changes of the kind may produce better results than prior inventions."). See MPEP 2144.05 II A. One of ordinary skill in the art before the effective filing date of the invention in view of the invention of Boyanov would have found it obvious to modify the invention of Tsai and perform routine experimentation to optimize the thickness of the first and second portions of the second etch stop in order to arrive at a desired etch profile between the off-target landing pad (the first portion) and the target landing pad (second portion) which will improve the ability of the unlanded portion of the via to not penetrate the first etch stop layer.
Applicant’s arguments, see pages 6-10, filed 07/06/26, with respect to the rejection(s) of claim(s) 1, 12, and 13 under 102 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of US 20200105591 (Lin et al).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VALERIE N NEWTON whose telephone number is (571)270-5015. The examiner can normally be reached M-F 8-5.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, CHAD DICKE can be reached at (571) 270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/VALERIE N NEWTON/ Examiner, Art Unit 2897 09/19/26
/CHAD M DICKE/ Supervisory Patent Examiner, Art Unit 2897
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