Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Election/Restrictions
1. Applicant’s election without traverse of Group I, which corresponds to claims 1-9 in the reply filed on 05/25/2026 is acknowledged. Therefore, claim 10 is withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim.
Double Patenting
2. The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-9 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1-13 of copending Application No. 18/632221. Although the claims at issue are not identical, they are not patentably distinct from each other because the claim 1 of the present application contains substantially the same subject matter as claim 1 of copending Application No. 18/632221 such as a package structure, comprising: a redistributed circuit structure, having opposite first surface and second surface; a plurality of chips, disposed on the second surface of the redistributed circuit structure; a second encapsulant, disposed on the second surface of the redistributed circuit structure and covers the chips; a plurality of supporting members, disposed on the first surface of the redistributed circuit structure and embedded in the redistributed circuit structure; a first encapsulant, disposed on the first surface of the redistributed circuit structure and covers the supporting members; and a plurality of connection terminals, connected to the supporting members.
Claim 2 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 2 of copending Application No. 18/632221. Claim 2 of the present application contains substantially the same subject matter as claim 2 of copending Application No. 18/632221, such as both claims have subject matter directed to a thickness of the second encapsulant is greater than a thickness of the first encapsulant.
Claim 3 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 4 of copending Application No. 18/632221. Claim 3 of the present application contains substantially the same subject matter as claim 4 of copending Application No. 18/632221, such as both claims have subject matter directed to a thickness of the first encapsulant is greater than a thickness of the plurality of supporting members.
Claim 4 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 5 of copending Application No. 18/632221. Claim 4 of the present application contains substantially the same subject matter as claim 5 of copending Application No. 18/632221, such as both claims have subject matter directed to each of the supporting members comprises a first portion and a second portion surrounding the first portion, and a thickness of the first portion is different from a thickness of the second portion.
Claim 5 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 7 of copending Application No. 18/632221. Claim 5 of the present application contains substantially the same subject matter as claim 7 of copending Application No. 18/632221, such as both claims have subject matter directed to a portion of the connection terminals is embedded in the first encapsulant.
Claim 6 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 8-10 of copending Application No. 18/632221. Claim 6 of the present application contains substantially the same subject matter as claims 8-10 of copending Application No. 18/632221, such as both claims have subject matter directed to the first encapsulant has a first encapsulating surface and a second encapsulating surface opposite to each other, the plurality of supporting members have a first supporting surface and a second supporting surface opposite to each other, and the first encapsulating surface, the first supporting surface, and the first surface of the redistributed circuit structure are coplanar, and wherein the second encapsulating surface and the second supporting surface are not coplanar; the second supporting surface is not flat; or the second supporting surface is an etched surface.
Claim 7 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 11 of copending Application No. 18/632221. Claim 7 of the present application contains substantially the same subject matter as claim 11 of copending Application No. 18/632221, such as both claims have subject matter directed to the first encapsulant has a second encapsulating surface away from the redistributed circuit structure, the plurality of supporting members have a second supporting surface far away from the redistributed circuit structure, and a roughness of the encapsulating surface is different from a roughness of the supporting surface.
Claim 8 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 12 of copending Application No. 18/632221. Claim 8 of the present application contains substantially the same subject matter as claim 12 of copending Application No. 18/632221, such as both claims have subject matter directed to a portion of the plurality of supporting members is overlapped with the plurality of chips.
Claim 9 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 13 of copending Application No. 18/632221. Claim 9 of the present application contains substantially the same subject matter as claim 13 of copending Application No. 18/632221, such as both claims have subject matter directed to a portion of the plurality of supporting members is electrically connected to the plurality of chips, and a portion of the plurality of supporting members is electrically separated from the plurality of chips.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
3. Claims 1-9 are rejected under 35 U.S.C. 102(a1) as being anticipated by Oh et al. (US 9,972,581; hereinafter Yu).
Regarding claim 1, Yu, in fig. 16, discloses a package structure comprising: a redistributed circuit structure (56C/58A) having a first surface (bottom surface of layer 66) and a second surface (bottom surface of layer 50) opposite to each other; a plurality of chips 36 disposed on the second surface of the redistributed circuit structure (56C/58A); a second encapsulant 48 disposed on the second surface of the redistributed circuit structure (56C/58A) and covering the plurality of chips 36; a plurality of supporting members 68 disposed on the first surface of the redistributed circuit structure (56C/58A); a first encapsulant 66 disposed on the first surface of the redistributed circuit structure (56C/58A) and covering the plurality of supporting members 68; and a plurality of connection terminals 70 connected to the plurality of supporting members 68.
Regarding claim 2, Yu discloses wherein a thickness of the second encapsulant 48 is greater than a thickness of the first encapsulant 66 (fig. 16).
Regarding claim 3, Yu discloses wherein a thickness of the first encapsulant 66 is greater than a thickness of the plurality of supporting members 68 (fig. 16).
Regarding claim 4, Yu discloses wherein each of the supporting members comprises a first portion and a second portion surrounding the first portion, and a thickness of the first portion is different from a thickness of the second portion (fig. 16).
Regarding claim 5, Yu discloses wherein a portion of the connection terminals is embedded in the first encapsulant (fig. 16).
Regarding claim 6, Yu discloses wherein the first encapsulant has a first encapsulating surface and a second encapsulating surface opposite to each other, the plurality of supporting members have a first supporting surface and a second supporting surface opposite to each other, and the first encapsulating surface, the first supporting surface, and the first surface of the redistributed circuit structure are coplanar, and wherein the second encapsulating surface and the second supporting surface are not coplanar; the second supporting surface is not flat; or the second supporting surface is an etched surface (fig. 16).
Regarding claim 7, Yu discloses wherein the first encapsulant has a second encapsulating surface away from the redistributed circuit structure, the plurality of supporting members have a second supporting surface far away from the redistributed circuit structure, and a roughness of the encapsulating surface is different from a roughness of the supporting surface (fig. 16).
Regarding claim 8, Yu discloses wherein a portion of the plurality of supporting members 68 is overlapped with the plurality of chips 36 (fig. 16).
Regarding claim 9, Yu discloses wherein a portion of the plurality of supporting members 68 is electrically connected to the plurality of chips 36, and a portion of the plurality of supporting members 68 is electrically separated from the plurality of chips 36 (fig. 16).
Conclusion
4. Any inquiry concerning this communication or earlier communications from the examiner should be directed to David Vu whose telephone number is (571) 272-1798. The examiner can normally be reached on Monday-Friday from 8:00am to 5:00pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempt to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Steven Loke H can be reached on (571) 272-1657. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/DAVID VU/
Primary Examiner, Art Unit 2818
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