Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
In response to applicant’s arguments filed 06/16/2026, the amendments to independent claims 1, 11 and 17 overcome the previous prior art rejection. However, upon further search and consideration a new rejection has been formulated below using Hwang et al. (US 20230005942) to teach the amended limitations.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2, and 6-10 are rejected under 35 U.S.C. 103 as being unpatentable over Mao et al (US 9673299 B2) in view of Takeshi et al (JP 2006310564) and in further view of Hwang et al (US 20230005942).
Mao et al teaches
[claim 1] A semiconductor device, comprising: a substrate that has a recess region therein (figure 3, col 5 lines 28-35, where element 301 is the substrate and element 500 is the recess in the substrate);
a gate electrode on a bottom surface of the recess region (figure 9, col 6 lines 12-17, where element 306 is the gate electrode on the bottom surface of the recess region);
a gate dielectric layer between the gate electrode and the bottom surface of the recess region (figure 9, col 6 lines 4-11, element 304 is the dielectric layer between the gate electrode [element 306] and the bottom of the recess),
a plurality of electrodes on laterally opposite sides of the gate electrode and on inner sidewalls of the recess region; a plurality of dielectric patterns between the plurality of shield electrodes and the inner sidewalls of the recess region (figure 9, col 6 lines 62- col 7 line 8, where element 302 is the dielectric pattern between the inner sidewall of the recess and the electrodes [element 303] which are situated laterally on opposite sides of the gate electrode);
a plurality of impurity regions in the substrate and on laterally opposite sides of the plurality of electrodes (col 7, lines 24-43, figure 15a, where element 308 is the impurity region on laterally opposite sides of the electrodes);
However, Mao et al does not specifically disclose
[claim 1] shield [electrodes], and a channel region in the substrate and below at least a portion of the bottom surface of the recess region, and a contact plug extending vertically and is connected to the gate electrode, wherein the plurality of impurity regions is higher than bottommost surfaces of the shield electrodes.
However, Takeshi et al does teach
[claim 1] shield [electrodes] (figure 16, paragraph 0029, where element 13 is the gate electrode with elements 18 are a plurality of shield electrodes, laterally opposite the gate electrode),
and a channel region in the substrate and below at least a portion of the bottom surface of the recess region (figure 16, paragraph 0027, where element 2 has a channel layer situated directly below the gate electrode and a bottom surface of the recess).
It would have been obvious to one of ordinary skill in the art at the time of filing to have modified the teachings of Mao et al to incorporate the teachings of Takeshi et al in order to situate the shield electrodes adjacent to the gate electrode in the trench to minimize parasitic capacitance between gate electrodes creating greater stability for operation.
However, Mao et al as modified does not specifically disclose
[claim 1] and a contact plug extending vertically and is connected to the gate electrode, wherein the plurality of impurity regions is higher than bottommost surfaces of the shield electrodes.
However, Hwang et al does teach
[claim 1] and a contact plug extending vertically and is connected to the gate electrode, wherein the plurality of impurity regions is higher than bottommost surfaces of the shield electrodes (figure 6, paragraph 0091, where element MC2 is a contact plug extending vertically and is connected to the gate electrode, where the gate electrode of transistor PTR is in place of the gate electrode of Mao et al as modified, where the impurity regions [situated in element MS of figure 6] is situated higher than the shield electrodes as read into from Mao et al as modified).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Mao et al as modified to incorporate the teachings of Hwang et al in order to connect the gate electrode through a vertical contact plug to operate the transistor through the gate electrode [gates are required to turn transistors on or off]).
Regarding claims 2, 6 and 10, Mao et al further teaches
[claim 2] The semiconductor device of claim 1, wherein the gate dielectric layer comprises: a first portion on the bottom surface of the recess region (figure 9, col 6 lines 4-11, where element 304 is the first portion of the gate dielectric layer and on the bottom surface of the recess region);
and a plurality of second portions between the gate electrode and the plurality of shield electrodes, each of the plurality of second portions extending vertically along a side of the gate electrode (figure 9, col 6 lines 4-11, where element 305 is the plurality of second portions of the gate dielectric layer and extending vertically up the along the side of the gate electrodes between the gate electrode [element 305] and the shield electrode [element 303] [note: shield electrode is read onto element 303 from Takeshi et al as noted above with Mao et al as modified]).
[claim 6] The semiconductor device of claim 1, wherein the plurality of impurity regions are higher than the bottom surface of the recess region (figure 11, col 6, lines 18-36, where element 308 is the impurity region and situated higher than the bottom surface of the recess).
[claim 10] The semiconductor device of claim 1, wherein each of the plurality of impurity regions includes an upper impurity region and a lower impurity region, wherein an impurity concentration of the upper impurity region is greater than an impurity concentration of the lower impurity region (figure 9, col 7 lines 24-43, where element 308 and 309 are two impurity regions of differing impurity types, element 308 is the lower impurity region and element 309 is the upper impurity region).
Regarding claims 5 and 9,
Mao et above teaches all of the limitations of the parent claim, claim 1, and Mao et al does not specifically disclose
[claim 5] The semiconductor device of claim 1, wherein each of the plurality of impurity regions has a conductivity type different from a conductivity type of the channel region.
[claim 9] The semiconductor device of claim 1, wherein the channel region extends along the bottom surface and the inner sidewalls of the recess region.
However, Takeshi et al further teaches
[claim 5] The semiconductor device of claim 1, wherein each of the plurality of impurity regions has a conductivity type different from a conductivity type of the channel region (figure 16, paragraph 0027, where element 2 has a channel layer situated directly below the gate electrode and a bottom surface of the recess and the inner sidewalls, where the channel region is a p-type depending on the type of transistor [could be n-type] and the impurity regions are of a ‘second conductivity type’ [col 7 lines 24-43, where element 308 is the second type, element 309 is the first type, thus 308 is opposite of what is required by the ‘first type’ where the channel region of Takeshi is established here as a first type]).
[claim 9] The semiconductor device of claim 1, wherein the channel region extends along the bottom surface and the inner sidewalls of the recess region (figure 16, paragraph 0027, where element 2 has a channel layer situated directly below the gate electrode and a bottom surface of the recess and the inner sidewalls).
It would have been obvious to one of ordinary skill in the art at the time of filing to have modified the teachings of Mao et al to incorporate the teachings of Takeshi et al in order to situate the channel layer below bottom of the recess to maximize the conductive path to form an inversion layer in the transistor.
Regarding claim 7,
Mao et al as modified teaches all of the limitations of the parent claim, claim 1, and further teaches
[claim 7] and the top surface of the gate electrode is vertically higher than a top surface of the substrate (figure 15a, col 7 lines 24-43, where element 306 has a top surface higher than element 301 [substrate]),
However, Mao et al as modified does not specifically teach
[claim 7] The semiconductor device of claim 1, wherein a top surface of the gate electrode is coplanar with top surfaces of the plurality of shield electrodes.
However, according to MPEP 2144.04 IV. CHANGES IN SIZE, SHAPE, OR SEQUENCE OF ADDING INGREDIENTS
A. Changes in Size/Proportion
In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955) (Claims directed to a lumber package "of appreciable size and weight requiring handling by a lift truck" were held unpatentable over prior art lumber packages which could be lifted by hand because limitations relating to the size of the package were not sufficient to patentably distinguish over the prior art.); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976) ("mere scaling up of a prior art process capable of being scaled up, if such were the case, would not establish patentability in a claim to an old process so scaled." 531 F.2d at 1053, 189 USPQ at 148.).
In Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device.
The gate electrode, element 306, is situated slightly lower than the shield electrodes [element 303, read into from Mao et al as modified above]. It would have been obvious to one of ordinary skill in the art at the time of filing to have modified the teachings of Mao et al to change the size of the gate electrode, element 306, to be coplanar with the shield electrodes in order to a specific design purpose as the device would not perform the essential function differently than what was disclosed in the prior art.
Regarding claim 8,
Mao et al as modified above teaches all of the limitations of the parent claim, claim 1, but does not specifically disclose
[claim 8] The semiconductor device of claim 1, wherein each of the plurality of shield electrodes extends laterally onto a top surface of the substrate and on the plurality of impurity regions.
However, a different embodiment of Mao et al does teach
[claim 8] The semiconductor device of claim 1, wherein each of the plurality of shield electrodes extends laterally onto a top surface of the substrate and on the plurality of impurity regions (figure 15b, col 7 lines 24-43, where element 311 extends from the shield electrodes [element 303, read into from Mao et al as modified above] onto the top of the substrate over the impurity regions [elements 308 and 309]).
It would have been obvious to one of ordinary skill in the art at the time of filing to have modified the teachings of Mao et al as modified above with a different emobidment of Mao et al to incorporate a conductive material that is attached to the shield electrodes in order to allow the electrodes to work [i.e. conduct] while maximizing space and situating the conductive material near and on top of the impurity regions.
Claim(s) 3 and 4 are rejected under 35 U.S.C. 103 as being unpatentable over Mao et al (US 9673299 B2) and Takeshi et al (JP 2006310564) in further view of Lee et al (US 10748905 B2).
Mao et al as modified teaches all of the limitations of the parent claims, claims 1 and 2, but does not specifically disclose
[claim 3] The semiconductor device of claim 2, wherein the first portion of the gate dielectric layer includes a material different from a material of the plurality of second portions of the gate dielectric layer.
[claim 4] The semiconductor device of claim 2, wherein each of the plurality of second portions of the gate dielectric layer includes an air gap.
However, Lee et al does teach
[claim 3] The semiconductor device of claim 2, wherein the first portion of the gate dielectric layer includes a material different from a material of the plurality of second portions of the gate dielectric layer (figure 6, col 13 lines 11-23, where element 130 is the gate dielectric layer and the first portion is element 142 and the second is element 146B with element 136v, which are made of differing materials).
[claim 4] The semiconductor device of claim 2, wherein each of the plurality of second portions of the gate dielectric layer includes an air gap (figure 6, col 13 lines 11-23, where element 130 is the gate dielectric layer and the first portion is element 142 and the second is element 146B with element 136V, where 136V is the air gap).
It would have been obvious to one of ordinary skill in the art to incorporate the teachings of Mao as modified to incorporate the teachings of Lee et al in order to buffer the dielectric layer to minimize parasitic capacitance with other portions [specifically other conductive elements] in the device to improve overall efficiency of the semiconductor device.
Claim(s) 11, 13, 14, 17, 19, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Son et al (US 20200027894 A1) in view of Mao et al (US 9673299 B2), Takeshi et al (JP 2006310564), and Hwang et al (US 20230005942).
Son et al teaches
[claim 11] A semiconductor device, comprising: a substrate that includes a cell array region and a contact region, the substrate having a recess region therein (figure 3, paragraph 0033, element 105 is the recess region in the substrate [element 101] and element 184 is the contact region);
a peripheral circuit structure on a top surface of the substrate and including a plurality of peripheral circuit transistors (figure 3, paragraph 0034, elements 120, 130, and CHS consist of the plurality of transistors on the substrate [element 101]);
a stack structure that includes a plurality of interlayer dielectric layers and a plurality of electrodes, the interlayer dielectric layers and the electrodes being alternately stacked on the peripheral circuit structure in a vertical direction perpendicular to the top surface of the substrate (figure 3, paragraphs 0033-0034, where elements 130, and 120, with CHS create the stack structure of interlayer dielectric layers [element 120] and electrodes [element 130], alternately stacked in a vertical direction perpendicular to the substrate [element 101]);
and a plurality of vertical channel structures that extend into the stack structure (figure 3, paragraphs 0033-0034, element CHS is the plurality of vertical channel structures [two are shown in the image]),
wherein the plurality of peripheral circuit transistors includes a first peripheral circuit transistor and a second peripheral circuit transistor (figure 3, paragraph 0045, where element 105 consists of a trench transistor, where the first peripherial transistor is shown in figure 3 and the second is on the back side [in the negative y-direction] of the semiconductor device [element 100]),
[claim 17] An electronic system, comprising: a semiconductor device that includes a substrate having a recess region therein, a peripheral circuit structure including a peripheral circuit transistor on the substrate (figure 3, paragraph 0045, where element 105 consists of a trench transistor in the substrate [element 101] on which a semiconductor device [element 100] is situated on the substrate),
a cell array structure including a stack structure on the peripheral circuit transistor (figure 3, paragraph 0034, where the stack of element 120 and 130 [repeating gate and dielectric layers] with the channels in the middle [element CHS] consists of the stack structure on the peripheral circuit transistor),
and an input/output pad electrically connected to the peripheral circuit transistor; and a controller electrically connected through the input/output pad to the semiconductor device, the controller configured to control the semiconductor device (figure 1, paragraph 0024, where element 50 is the controller with an input/output through the Bit-Line [element BL] connected to the circuit transistor through element 187 [conductive layer that read/writes onto the memory array and connected to the peripheral circuit transistor]),
However, Son et al does not specifically disclose
[claim 11] and wherein the first peripheral circuit transistor includes: a first gate electrode on a bottom surface of the recess region; and a plurality of shield electrodes on laterally opposite sides of the first gate electrode and inner sidewalls of the recess region, a contact plug that extends vertically and is connected to the first gate electrode.
[claim 17] wherein the peripheral circuit transistor includes: a gate dielectric layer on a bottom surface of the recess region; a gate electrode on the gate dielectric layer; a plurality of dielectric patterns on inner sidewalls of the recess region; and a plurality of electrodes between the plurality of dielectric patterns and the gate electrode, a contact plug that extends vertically and is connected to the gate electrode
However, Mao et al does teach
[claim 11] and wherein the first peripheral circuit transistor includes: a first gate electrode on a bottom surface of the recess region; and a plurality of electrodes on laterally opposite sides of the first gate electrode and inner sidewalls of the recess region (figure 9, col 6 lines 62- col 7 line 8, where element 306 is the gate electrode, and element 303 is the electrodes laterally opposite the first gate electrode and on the inner sidewalls of the recess);
[claim 17] wherein the peripheral circuit transistor includes: a gate dielectric layer on a bottom surface of the recess region; a gate electrode on the gate dielectric layer; a plurality of dielectric patterns on inner sidewalls of the recess region; and a plurality of electrodes between the plurality of dielectric patterns and the gate electrode (figure 9, col 6 lines 62- col 7 line 8, where element 306 is the gate electrode, and element 303 is the electrodes laterally opposite the first gate electrode and on the inner sidewalls of the recess);
It would have been obvious to one of ordinary skill in the art at the time of filing to have modified the teachings of Son et al to incorporate the teachings of Mao in order to maximize physical space by locating a transistor within a recess in the substrate instead of situated in another space on the substrate.
However, Son et al as modified does not specifically disclose
[claims 11 & 17] shield [electrodes], a contact plug that extends vertically and is connected to the first gate electrode.
However, Takeshi et al does teach
[claims 11 & 17] shield [electrodes] (figure 16, paragraph 0029, where element 13 is the gate electrode with elements 18 are a plurality of shield electrodes, laterally opposite the gate electrode),
It would have been obvious to one of ordinary skill in the art at the time of filing to have modified the teachings of Son et al as modified to incorporate the teachings of Takeshi et al in order to situate the shield electrodes adjacent to the gate electrode in the trench to minimize parasitic capacitance between gate electrodes creating greater stability for operation.
However, son et al as modified does not specifically disclose
[claims 11 & 17] a contact plug that extends vertically and is connected to the first gate electrode.
However, Hwang et al teaches
[claims 11 & 17] a contact plug that extends vertically and is connected to the first gate electrode (figure 6, paragraph 0091, where element MC2 is a contact plug extending vertically and is connected to the gate electrode, where the gate electrode of transistor PTR is in place of the gate electrode of Mao et al as modified, where the impurity regions [situated in element MS of figure 6] is situated higher than the shield electrodes as read into from Mao et al as modified).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Son et al as modified to incorporate the teachings of Hwang et al in order to connect the gate electrode through a vertical contact plug to operate the transistor through the gate electrode [gates are required to turn transistors on or off]).
Regarding claim 15,
Mao further teaches
[claim 15] The semiconductor device of claim 11, wherein a top surface of the first gate electrode is vertically lower than the top surface of the substrate (figure 9, col 7 lines 17-23, where element 306 is lower than a top surface of the substrate [element 301]).
Regarding claim 13, 14, 19 and 20
Mao further teaches
[claim 13] The semiconductor device of claim 11, wherein the first peripheral circuit transistor further includes: a gate dielectric layer between the first gate electrode and the bottom surface of the recess region (figure 9, col 6 line 4-11, where element 304 is the gate dielectric layer situated between the first gate electrode [element 306] and the bottom of the recess);
a plurality of impurity regions extending in a horizontal direction parallel to the top surface of the substrate on opposite sides of the recess region (figure 9, col 6 lines 18-36, where element 308 is the impurity regions extending in a horizontal direction parallel to the top surface of the substrate on opposite sides of the recess regions);
[claim 14] The semiconductor device of claim 13, wherein the gate dielectric layer extends between the first gate electrode and the plurality of shield electrodes (figure 9, col 5 lines 35-42, where element 302 is the dielectric situated between the gate electrode [element 306] and the shield electrodes [element 303, read into from Son et al as noted above that element 303 is a shield electrode and not a simple electrode]).
[claim 19] The electronic system of claim 17, wherein the peripheral circuit transistor further includes: a plurality of impurity regions extending in a horizontal direction parallel to a top surface of the substrate on opposite sides of the recess region (figure 9, col 6 lines 18-36, where element 308 is the impurity regions extending in a horizontal direction parallel to the top surface of the substrate on opposite sides of the recess regions);
However, Son et al as modified with Mao does not specifically teach
[claim 13] and a channel region below the bottom surface of the recess region
[claim 19] and a channel region below the bottom surface of the recess region, wherein the plurality of impurity regions have a conductivity type different from a conductivity type of the channel region.
[claim 20] The electronic system of claim 17, wherein top surfaces of the plurality of shield electrodes are vertically higher than a top surface of the substrate.
However, Takeshi et al does teach
[claim 13] and a channel region below the bottom surface of the recess region (figure 16, paragraph 0027, where element 2 has a channel layer situated directly below the gate electrode and a bottom surface of the recess and the inner sidewalls).
[claim 19] and a channel region below the bottom surface of the recess region, wherein the plurality of impurity regions have a conductivity type different from a conductivity type of the channel region (figure 16, paragraph 0027, where element 2 has a channel layer situated directly below the gate electrode and a bottom surface of the recess and the inner sidewalls, where the channel region is a p-type depending on the type of transistor [could be n-type] and the impurity regions are of a ‘second conductivity type’ [col 7 lines 24-43, where element 308 is the second type, element 309 is the first type, thus 308 is opposite of what is required by the ‘first type’ where the channel region of Takeshi is established here as a first type]).
[claim 20] The electronic system of claim 17, wherein top surfaces of the plurality of shield electrodes are vertically higher than a top surface of the substrate (figure 16, where the top of element 18 is higher than the substrate).
It would have been obvious to one of ordinary skill in the art at the time of filing to have modified the teachings of Mao et al to incorporate the teachings of Takeshi et al in order to situate the channel layer below bottom of the recess to maximize the conductive path to form an inversion layer in the transistor.
Regarding claim 12,
Son et al as modified teaches all of the limitations of the parent claim, claim 11, but does not specifically teach
[claim 12] The semiconductor device of claim 11, wherein the second peripheral circuit transistor includes a second gate electrode on the top surface of the substrate.
However, according to MPEP 2144.04 VI. REVERSAL, DUPLICATION, OR REARRANGEMENT OF PARTS
B. Duplication of Parts
In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960) (Claims at issue were directed to a water-tight masonry structure wherein a water seal of flexible material fills the joints which form between adjacent pours of concrete. The claimed water seal has a "web" which lies in the joint, and a plurality of "ribs" projecting outwardly from each side of the web into one of the adjacent concrete slabs. The prior art disclosed a flexible water stop for preventing passage of water between masses of concrete in the shape of a plus sign (+). Although the reference did not disclose a plurality of ribs, the court held that mere duplication of parts has no patentable significance unless a new and unexpected result is produced.).
Mao et al discloses a single gate electrode in the first peripheral circuit, but does not explicitly teach a second gate electrode in a second peripheral circuit. However, it would have been obvious to one of ordinary skill in the art at the time of filing to have used the teachings of Mao et al, with a gate electrode [element 306] over the substrate [element 301], per figure 15a, in the second peripheral transistor of Son et al as a duplication of parts. Thus the exact same part used in one location is also used in another location for the same purpose.
Regarding claim 16,
Son et al teaches all of the limitations of the parent claim, claim 11, but the specific embodiment of Mao et al does not teach
[claim 16] The semiconductor device of claim 11, wherein the plurality of shield electrodes extend from the inner sidewalls of the recess region onto the top surface of the substrate.
However, a different embodiment of Mao et al does teach
[claim 16] The semiconductor device of claim 11, wherein the plurality of shield electrodes extend from the inner sidewalls of the recess region onto the top surface of the substrate (figure 15b, col 7 lines 24-43, where element 311 extends from the shield electrodes [element 303, read into from Mao et al as modified above] onto the top of the substrate over the impurity regions [elements 308 and 309]).
It would have been obvious to one of ordinary skill in the art at the time of filing to have modified the teachings of Son et al as modified above with a different emobidment of Mao et al to incorporate a conductive material that is attached to the shield electrodes in order to allow the electrodes to work [i.e. conduct] while maximizing space and situating the conductive material near and on top of the impurity regions.
Claim(s) 18 is rejected under 35 U.S.C. 103 as being unpatentable over Son et al (US 20200027894 A1) in view of Mao et al (US 9673299 B2) and Takeshi et al (JP 2006310564), and Hwang et al (US 20230005942) as applied to claim 17 above, and in further view of Yu et al (US 20180122906 A1).
Son et al as modified above teaches all of the limitations of the parent claim, claim 17, but does not specifically disclose
[claim 18] The electronic system of claim 17, wherein the peripheral circuit structure includes a first bonding pad electrically connected to the peripheral circuit transistor, and the cell array structure includes a second bonding pad in contact with the first bonding pad.
However, Yu et al does teach
[claim 18] The electronic system of claim 17, wherein the peripheral circuit structure includes a first bonding pad electrically connected to the peripheral circuit transistor (figure 21, paragraph 0214, where element 38 is in the position of the peripheral circuit transistor of Son et al as modified, and contains a bonding pad [guard rail] that is electrically connected to the transistor [situated where element 38 is in the middle with semiconductor layer 112 below]),
and the cell array structure includes a second bonding pad in contact with the first bonding pad (figure 21, paragraph 0219, where element 46L directly above and connected to element 38 in the middle [beneath element 79’] is the second bonding pad and in contact with the first bonding pad).
It would have been obvious to one of ordinary skill in the art at the time of filing to have modified the teachings of Son et al as modified to incorporate the teachings of Yu et al in order to connect the control line to the peripheral circuit transistor so the transistor can function and work through the control line.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANDREW ZABEL whose telephone number is (703)756-4788. The examiner can normally be reached M-F 9-5PM ET.
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/ANDREW JOHN ZABEL/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
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