CTNF 18/428,092 CTNF 88013 DETAILED ACTION This Office Action is in response to Applicant’s application 18/428,092 filed on January 31, 2024 in which claims 1 to 20 are pending. Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Drawings The drawings submitted on January 31, 2024 have been reviewed and accepted by the Examiner. Information Disclosure Statement The Information Disclosure Statements (IDS), filed on May 1, 2025 and October 22, 2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosed therein has been considered by the Examiner. Notation References to patents will be in the form of [C:L] where C is the column number and L is the line number. References to pre-grant patent publications will be to the paragraph number in the form of [xxxx]. Claim Rejections - 35 USC § 102 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-12-aia AIA (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 07-15 AIA PNG media_image1.png 544 926 media_image1.png Greyscale Claim s 1-2 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by U.S. 20221/0050326 (Choi) . Regarding claim 1 and referring to annotated Figure 2, Choi discloses a stacked integrated circuit (IC) device comprising: a first memory die, 200 [0026] as annotated, coupled to a substrate, 100 [0021]; a second memory die, 200 [0026] as annotated, coupled to the substrate, 100 as shown; and a logic die, 400 [0021], electrically connected, face-to-face, to the first memory die and the second memory die, as shown, and electrically connected to the substrate by conductors, 300 [0028], that extend through a region between the first memory die and the second memory die, as shown. Regarding claim 2 which depends upon claim 1, Choi teaches a plurality of electrical interconnects, 310 [0030], on a face of the logic die, as shown, the plurality of electrical interconnects including: first electrical interconnects in a first memory interconnect region, as annotated, wherein the first electrical interconnects have a first characteristic length, as annotated and shown; second electrical interconnects, 310 as annotated, in a second memory interconnect region, as annotated and shown, wherein the second electrical interconnects have the first characteristic length, as shown; and the conductors, 300, wherein the conductors have a second characteristic length, as annotated and shown, greater than the first characteristic length, as shown . 07-15 AIA PNG media_image2.png 556 745 media_image2.png Greyscale Claim s 14-16 and are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by U.S. 2023/0207475 (Brun) . Regarding claim 14 and referring to Figures 1A and 5E, Brun discloses a stacked IC device comprising: PNG media_image3.png 483 746 media_image3.png Greyscale a first memory die, 150 [0022] as annotated, coupled to a substrate, 511 [0062] as shown; a second memory die, 150 [0022] as annotated, coupled to the substrate, 511 [0062] as shown; a first logic die, 141 [0022], electrically connected, face-to-face, to the first memory die, as shown and described at [0007, 18]; a second logic die, 142 [0022], electrically connected, face-to-face, to the second memory die, as shown and described at [0007, 18]; and conductors, 149 [0021], extending through a region between the first memory die and the second memory die, as shown, and electrically connecting the first logic die and the second logic die to the substrate, as shown. Regarding claim 15 which depends upon claim 14, Brun teaches a patch component, 160 described as a bridge die at [0021], coupled to the substrate, as shown, wherein the conductors are located in a body of the patch component, as shown. Regarding claim 16 which depends upon claim 15, Brun teaches the first logic die and the second logic die are electrically connected to one another by one or more conductive paths through the patch component at [0021] . Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-23-aia AIA The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. 07-21-aia AIA Claim s 1-3, 5, 7-10 and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Brun and Choi . Regarding claim 1 and referring to annotated Figures 1A and 5E, Brun discloses a stacked integrated circuit (IC) device comprising: a first memory die, 150 [0022] / 550 [0057] as annotated, coupled to a substrate, 511 [0062], as shown; a second memory die, 150 [0022] / 550 [0057] as annotated, coupled to the substrate, 511 [0062] as shown; and a logic die, e.g., 141 [0022] / 541 [0060] as annotated, electrically connected, face-to-face, as shown and described at [0007, 18], to the first memory die, as shown, and electrically connected to the substrate by conductors, 149 [0020] / 544, that extend through a region between the first memory die and a second memory die, as shown. Arguably, Brun does not teach a logic die electrically connected, face-to-face to the second memory die. Referring to the discussion at claim 1, Choi teaches a logic die electrically connected, face-to-face to the second memory die. Choi teaches this configuration has excellent reliability at [0033]. An artisan would find it desirable to configure a package with excellent reliability. Accordingly, it would have been obvious to a person of ordinary skill in the art at the time of Applicant’s invention to configure the device of claim 1 with the logic die electrically connected, face-to-face to the second memory die to improve package reliability and because the combination of familiar elements according to known methods is likely to be obvious when it does no more than yield predictable results. KSR International Co. v. Teleflex Inc ., 550 U.S. 398, 416 (2007). Regarding claim 2 which depends upon claim 1, Brun teaches a plurality of electrical interconnects 144 [0020] / 549, on a face of the logic die, as shown, the plurality of electrical interconnects including: first electrical interconnects, as annotated, in a first memory interconnect region, as shown, wherein the first electrical interconnects have a first characteristic length, as annotated; second electrical interconnects, as annotated, in a second memory interconnect region, as shown, wherein the second electrical interconnects have the first characteristic length, as shown; and the conductors, wherein the conductors have a second characteristic length greater than the first characteristic length, as annotated and shown. Regarding claim 3 which depends upon claim 1, further comprising a patch component, 160 [0021], coupled to the substrate, as shown, wherein the conductors are located in a body of the patch component, as shown where 161 is a TSV [0021]. Regarding claim 5 which depends upon claim 3, Brun teaches the body includes silicon, and the conductors include through silicon vias where an artisan would understand TSV as referring to through silicon vias. Regarding claim 7 which depends upon claim 3, Brun teaches a face of the first memory die is substantially coplanar with a face of the patch component at Figure 1A. Regarding claim 8 which depends upon claim 3, Brun teaches the first memory die, the second memory die, the logic die, the patch component, or combinations thereof, are at least partially encapsulated in mold compound 147 [0021]. Regarding claim 9 which depends upon claim 3, Brun teaches a second logic die, e.g. 142 [0022], electrically connected to the logic die by one or more conductive paths through the patch component, as described at [0021]. Regarding claim 10 which depends upon claim 1, Brun teaches one or more redistribution layers, 146 [0020], coupled to the logic die, as shown, wherein electrical connections of the logic die to the first memory die and to the second memory die include conductive paths in the one or more redistribution layers, as shown where Examiner notes it is the nature of RDL to have conductive paths….. Regarding claim 18 Brun discloses at Figure 1A and 5E a method comprising: attaching a first memory die, 150 [0022] as annotated, to a substrate, 511 [0062]; attaching a second memory die, 150 [0022] as annotated, to the substrate, as shown; and electrically connecting a logic die, 141 [0022], to the substrate, as shown, to the first memory die, as shown, and to the second memory die, as shown, such that the logic die is oriented face-to-face with the first memory die and the second memory die, as shown and described at [0007, 18], and conductors, 149 [0021] that electrically connect the logic die to the substrate extend through a region between the first memory die and the second memory die. Brun does not teach electrically connecting a logic die to the second memory die, such that the logic die is oriented face-to-face with the second memory die. Choi teaches electrically connecting a logic die, 400, to the substrate, 100, to the first memory die, 200, and to the second memory die, 200, such that the logic die is oriented face-to-face with the first memory die and the second memory die, a and conductors, 300, that electrically connect the logic die to the substrate extend through a region between the first memory die and the second memory die. Choi teaches this method produces a package with improved reliability at [0033]. According it would have been obvious to a person of ordinary skill in the art at the time of Applicant’s invention to configure the method of claim 18 by electrically connecting a logic die to the second memory die, such that the logic die is oriented face-to-face with the second memory die, as taught by Choi, to produce a package with improved reliability as taught by Choi and because the combination of familiar elements according to known methods is likely to be obvious when it does no more than yield predictable results. KSR International Co. v. Teleflex Inc ., 550 U.S. 398, 416 (2007). Regarding claim 19 which depends upon claim 18, Brun teaches the conductors, 161, are disposed in a body of a patch component, 160, and wherein electrically connecting the logic die to the substrate comprises: electrically connecting the patch component to the substrate in the region between the first memory die and the second memory die, as shown; and electrically connecting the logic die to the patch component, as shown and described at [0021]. Regarding claim 20 which depends upon claim 18, Brun teaches electrically connecting a second logic die, 142 [0022], to the substrate, 511 [0062], and, face-to-face to the first memory die, as shown and described at [0007. 18]; and electrically connecting the second logic die to the logic die by one or more conductive paths through the conductors, as shown and described at [0021] . 07-21-aia AIA PNG media_image4.png 529 746 media_image4.png Greyscale Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Brun and U.S. 2025/0316554 (Chen) . Regarding claim 6 which depends upon claim 3, Brun teaches the patch component is a bridge die. Brun does not teach the patch component includes active circuit components, passive circuit components, or both. Chen is directed to stacked ICs using bridge die. At [0022], Chen teaches is configured with active circuit components and/or passive circuit components. Taken as a whole, the prior art is directed to stacked die for HBM memory. Chen teaches Brun’s bridge die may be configured with active or passive devices. An artisan would recognize the utility of active or passive devices to improve signal integrity between the CPUs and the memory die, thus improving the bandwidth of the device. Likewise, the use of passive devices in the bridge die improves power deliver to the CPU die. Accordingly, it would have been obvious to person of ordinary to a person of ordinary skill in the art at the time of Applicant’s invention to configure the device of claim 3 wherein the patch component includes active circuit components, passive circuit components, or both to improve power delivery and signal integrity and because the combination of familiar elements according to known methods is likely to be obvious when it does no more than yield predictable results. KSR International Co. v. Teleflex Inc ., 550 U.S. 398, 416 (2007) . Allowable Subject Matter 12-151-08 AIA 07-43 12-51-08 Claim s 4, 11-13 and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. 13-03-01 AIA The following is a statement of reasons for the indication of allowable subject matter: Regarding claim 4 which depends upon claim 3, wherein the body includes a polymer in which the conductors are embedded . Regarding claim 11 which depends upon claim 1, further comprising wire bonds electrically connecting contacts on a face of the first memory die to contacts of the substrate. Regarding claim 12 which depends upon claim 1, further comprising a third memory die coupled in a stacked configuration to the first memory die, and a plurality of wire bonds electrically connecting contacts on a face of the third memory die to contacts of the substrate. Regarding claim 13 which depends upon claim 1, wherein the first memory die is coupled to a recess in the substrate. Regarding claim 17 which depends upon claim 14, wherein the first memory die is coupled to a recess in the substrate . Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure is listed on the notice of references cited . Any inquiry concerning this communication or earlier communications from the examiner should be directed to Joe Schoenholtz whose telephone number is (571)270-5475. The examiner can normally be reached M-Thur 7 AM to 7 PM PST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ms. Yara Green can be reached at (571) 272-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /J.E. Schoenholtz/Primary Examiner, Art Unit 2893 Application/Control Number: 18/428,092 Page 2 Art Unit: 2893 Application/Control Number: 18/428,092 Page 3 Art Unit: 2893 Application/Control Number: 18/428,092 Page 4 Art Unit: 2893 Application/Control Number: 18/428,092 Page 5 Art Unit: 2893 Application/Control Number: 18/428,092 Page 6 Art Unit: 2893 Application/Control Number: 18/428,092 Page 7 Art Unit: 2893 Application/Control Number: 18/428,092 Page 8 Art Unit: 2893 Application/Control Number: 18/428,092 Page 9 Art Unit: 2893 Application/Control Number: 18/428,092 Page 10 Art Unit: 2893 Application/Control Number: 18/428,092 Page 11 Art Unit: 2893 Application/Control Number: 18/428,092 Page 12 Art Unit: 2893