DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3, and 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20170345916 (Hong et al) in view of US 20180019132 (Mauder et al) and US 5747831 (Loose et al).
Considering claim 1, Hong discloses a method of fabricating an integrated circuit (IC) (Figs. 3-10), comprising: forming a corrugated channel structure over a semiconductor substrate (Figs. 4-5, note that the substrate is patterned to form a ridge-trench alternating pattern (the definition of a corrugated structure)) , the corrugated channel structure including a bottom semiconductor surface and a sidewall (101a and 101b) between the semiconductor top surface (Fig. 7, [0018]- [0019], and [0027], note that the fins are formed from substrate 100 which is disclosed as being made of a semiconductor material); forming a top oxide cap (110/110a) over the top surface (Fig. 8 and [0025]) and a bottom oxide (130) . . . over the bottom semiconductor surface (Fig. 7); implanting a first dopant in the sidewall in a first implant ([0046]); removing the top oxide cap (Fig. 10 and [0054]) . . . ; and implanting a second dopant in the top semiconductor surface ([0044]).
Hong does not disclose that the bottom oxide is a bottom oxide cap, removing the bottom oxide cap, or implanting a second dopant in the bottom semiconductor surface. However, Mauder discloses a method of forming a semiconductor device having a corrugated channel structure (Figs. 12A-12D) with trenches (12) and mesas (13) having a protective structure (4) formed over the top of the mesas and the bottom of the trenches concurrently (Fig. 12A and [0076]) followed by multiple implanting steps (Figs. 12A-12D) and subsequent removal of the protective layer ([0079]). In re Burhans, 154 F.2d 690, 69 USPQ 330 (CCPA 1946) (selection of any order of performing process steps is prima facie obvious in the absence of new or unexpected results); See MPEP 2144.04 IV C. Therefore absent evidence that the order of performing the process steps (concurrently or sequentially) provides a new or unexpected result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to concurrently form the top oxide and bottom oxide in view of the process of Mauder.
Additionally, Loose discloses a semiconductor manufacturing method in which dopants are implanted into a bottom semiconductor surface of a fin structure (Fig. 2c and col. 3 lines 11-19) and such configuration provides a structure for field-effect transistors in which a sufficient pinch-off behavior can be achieved in the channel zone by the smallest possible gate voltage. Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the implantation process to implant the dopants additionally into the bottom semiconductor surface in order to achieve the aforementioned advantage.
Referring to claim 3, Hong in view of Mauder and Loose discloses further comprising removing the bottom oxide cap concurrently with removing the top oxide cap (Mauder [0079]).
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20170345916 (Hong et al) in view of US 20180019132 (Mauder et al), and US 5747831 (Loose et al), as applied to claim 1 above, and further in view of US 20230164986 (Yu et al).
Regarding claim 4, Hong in view of Mauder and Loose discloses wherein the top oxide cap is formed by first forming a . . .oxide layer over the top surface and the sidewall surface, and then selectively removing the . . . oxide layer over the sidewall surface (Mauder [0076]).
Hong in view of Mauder and Loose does not disclose the processing order of the oxide layer or that it is a conformal oxide layer. Yu discloses a method of forming an oxide layer (13) over a semiconductor structure and then etching to selectively remove portions of the oxide layer over the sidewalls (Figs 1A-1C and [0030]). In re Burhans, 154 F.2d 690, 69 USPQ 330 (CCPA 1946) (selection of any order of performing process steps is prima facie obvious in the absence of new or unexpected results); See MPEP 2144.04 IV C. Therefore absent evidence that the order of performing the process steps provides a new or unexpected result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to form the oxide layer over the semiconductor structures and selectively remove portions of the oxide layer on the sidewalls to arrive at the structure of Hong in view of Mauder and Loose.
Claim(s) 10 and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20170345916 (Hong et al) in view of US 20180019132 (Mauder et al), US 20230164986 (Yu et al), and US 5747831 (Loose et al).
Pertaining to claim 10, Hong discloses a method of fabricating an integrated circuit (IC) (Figs. 3-10), comprising: forming a corrugated channel structure over a semiconductor substrate (Figs. 4-5, note that the substrate is patterned to form a ridge-trench alternating pattern (the definition of a corrugated structure)), the plurality of corrugated channel structures separated by respective trenches (Fig. 5) formed between adjacent corrugated channel structures (101), each trench including a bottom semiconductor surface and each corrugated channel structure including a first sidewall, a second sidewall (101a and 101b) and a top semiconductor surface (Fig. 7, [0018]- [0019], and [0027], note that the fins are formed from substrate 100 which is disclosed as being made of a semiconductor material); forming a . . . oxide layer (110/110a and 130) over the corrugated channel structures . . .; selectively removing the conformal oxide layer from the first and second sidewalls of respective corrugated channel structures ([0030]-[0031]), wherein a remaining portion of the . . .oxide layer forms a top oxide cap (110/110a) over the top surface of each respective corrugated channel structure and a bottom oxide cap (130) over the bottom surface of each respective trench (Fig. 6); implanting a first dopant in the first and second sidewalls of the respective corrugated channel structures using a nonzero beamline tilt angle with respect to a surface normal of the semiconductor substrate ([0046]);.removing the top . . . oxide cap . . . (Fig. 10); and implanting a second dopant in the top semiconductor surfaces of the respective corrugated channel structures and in the bottom . . .surfaces of the respective trenches ([0044]) using a beamline tilt angle about parallel to the surface normal of the semiconductor substrate.
Hong does not disclose that the oxide layer is a conformal oxide layer and over the top and bottom surfaces, removing the . . . . bottom oxide caps, and implanting a second dopant in the bottom semiconductor surfaces. However, Mauder discloses a method of forming a semiconductor device having a corrugated channel structure (Figs. 12A-12D) with trenches (12) and mesas (13) having an protective structure (4) formed over the corrugated channel structures and subsequently etched to leave the protective layer on the top of the mesas and the bottom of the trenches concurrently (Fig. 12A and [0076]) followed by multiple implanting steps (Figs. 12A-12D) and subsequent removal of the protective layer ([0079]). Yu discloses a method of forming an oxide layer (13) over a semiconductor structure and then etching to selectively remove portions of the oxide layer over the sidewalls (Figs 1A-1C and [0030]). In re Burhans, 154 F.2d 690, 69 USPQ 330 (CCPA 1946) (selection of any order of performing process steps is prima facie obvious in the absence of new or unexpected results); See MPEP 2144.04 IV C. Therefore absent evidence that the order of performing the process steps (concurrently or sequentially) provides a new or unexpected result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to form the oxide layer over the semiconductor structures, remove portions on the sidewalls, and then concurrently remove the top oxide and bottom oxide in view of the process of Mauder and Yu.
Additionally, Loose discloses a semiconductor manufacturing method in which dopants are implanted into a bottom semiconductor surface of a fin structure (Fig. 2c and col. 3 lines 11-19) and such configuration provides a structure for field-effect transistors in which a sufficient pinch-off behavior can be achieved in the channel zone by the smallest possible gate voltage. Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the implantation process to implant the dopants additionally into the bottom semiconductor surface in order to achieve the aforementioned advantage.
As to claim 12, Hong in view of Mauder, Yu, and Loose disclose wherein the conformal oxide layer is comprised of horizontal portions having a first density formed over the top surfaces and the bottom surfaces, and vertical portions having a second density less than the first density formed over the first and second sidewalls of the respective corrugated channel structures (Hong Fig. 7 and Mauder Fig. 12A, note that the oxide layer is removed from the sidewall leaving the density of the oxide layer at zero which is less than the density of the oxide layer on the top and bottom of the corrugated structures).
Claim(s) 16, 18, and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20130183804 (Wang et al) in view of US 20180019132 (Mauder et al) and US 5747831 (Loose et al).
Concerning claim 16, Wang discloses a method of fabricating an integrated circuit (IC) (Figs. 5-7A), comprising: forming a . . . corrugated channel structures over a semiconductor substrate (Fig. 5, note that the substrate is patterned to form a ridge-trench alternating pattern (the definition of a corrugated structure)), , the . . . corrugated channel structures separated by respective trenches formed . . . (Fig. 5), each trench including a bottom semiconductor and each corrugated channel structure including a first sidewall, a second sidewall and a top semiconductor surface (Fig. 5A); selectively forming a top oxide cap (12a) over the top surface of . . . corrugated channel structure ([0020]) and a bottom oxide cap (18a) over the bottom of each respective trench ([0021]); implanting one or more dopants in the first and second sidewalls of the respective corrugated channel structures using one or more beamline tilt angles with respect to a surface normal of the semiconductor substrate (Fig. 6 and [0025]); removing the top . . . oxide caps (Fig. 7A and [0026]); and implanting, in a vertical implant, one or more dopants in the top semiconductor surfaces of the respective corrugated channel structures and in the bottom . . . of the respective trenches ([0027]).
Wang does not disclose forming a plurality of corrugated channel structures, removing the top and bottom oxide caps, or implanting, . . .one or more dopants . . . in the bottom semiconductor surfaces. However, Mauder discloses a method of forming a semiconductor device having a plurality of corrugated channel structure (Figs. 12A-12D) with trenches (12) and mesas (13) having a protective structure (4) formed over the top of the mesas and the bottom of the trenches concurrently (Fig. 12A and [0076]) followed by multiple implanting steps (Figs. 12A-12D) and subsequent removal of the protective layer ([0079]). In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966) (The court held that the configuration of the claimed disposable plastic nursing container was a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed container was significant.) Therefore absent evidence that claimed configuration is significant it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the configuration of Wang to include a plurality of corrugated channel structures with the top oxide and bottom oxide subsequently removed after an implant process in view of the process of Mauder.
Additionally, Loose discloses a semiconductor manufacturing method in which dopants are implanted into a bottom semiconductor surface of a fin structure (Fig. 2c and col. 3 lines 11-19) and such configuration provides a structure for field-effect transistors in which a sufficient pinch-off behavior can be achieved in the channel zone by the smallest possible gate voltage. Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the implantation process to implant the dopants additionally into the bottom semiconductor surface in order to achieve the aforementioned advantage.
Continuing to claim 18, Wang in view of Mauder and Loose discloses wherein the top oxide caps and the bottom oxide caps have a first thickness greater than a second thickness of sidewall oxide portions formed over the first and second sidewalls of the respective corrugated channel structures (Wang Fig. 7 and Mauder Fig. 12 A, note that the oxide layer is removed from the sidewall leaving the thickness of the oxide layer zero on the sidewalls which is less than the thickness of the top and bottom oxide caps on the corrugated structures).
Considering claim 19, Wang in view of Mauder and Loose discloses wherein the top oxide caps and the bottom oxide caps are removed by a wet etch (Wang [0026], note that the modified process of Wang in view of Mauder removes both the top and bottom oxide caps therefore the process in Wang that removes the top oxide cap is the same that removes the bottom oxide cap of the modified configuration of Wang in view of Mauder).
Claim(s) 5 and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20170345916 (Hong et al) in view of US 20180019132 (Mauder et al) and US 5747831 (Loose et al) as applied to claim 1 above, and further in view of US 20130183804 (Wang et al).
Referring to claims 5 and 8, Hong in view of Mauder and Loose discloses etching the oxide caps and conformal oxide layer.
Hong in view of Mauder and Loose is silent as to the etching process and therefore does not disclose wherein the conformal oxide layer is selectively removed over the sidewall surface by a wet etch or wherein the top oxide cap and the bottom oxide cap are removed by a wet etch. However, Wang discloses a corrugated channel structure that utilizes a top and bottom oxide layer (Figs. 5-7A) and that the etching/removal of these oxide layers is done by a wet etch ([0026]). The selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945). See MPEP 2144.07. Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use wet etching to remove the oxide layers of Hong in view of Mauder because of its known suitability of removing such layers.
Claim(s) 13 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20170345916 (Hong et al) in view of US 20180019132 (Mauder et al), US 20230164986 (Yu et al), and US 5747831 (Loose et al) as applied to claim 10 above, and further in view of US 20130183804 (Wang et al).
According to claims 13 and 14, Hong in view of Mauder, Yu, and Loose disclose etching the oxide caps and conformal oxide layer.
Hong in view of Mauder, Yu, and Loose is silent as to the etching process and therefore does not disclose wherein the conformal oxide layer is selectively removed from the first and second sidewalls of the respective corrugated channel structures using a wet etch, or wherein the top oxide caps and the bottom oxide caps are removed by a wet etch. However, Wang discloses a corrugated channel structure that utilizes a top and bottom oxide layer (Figs. 5-7A) and that the etching/removal of these oxide layers is done by a wet etch ([0026]). The selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945). See MPEP 2144.07. Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use wet etching to remove the oxide layers of Hong in view of Mauder because of its known suitability of removing such layers.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20170345916 (Hong et al) in view of US 20180019132 (Mauder et al), US 5747831 (Loose et al), and US 20230164986 (Yu et al).as applied to claim 4 above, and further in view of US 20180374754 (Lee et al).
Regarding claim 6, Hong in view of Mauder, Loose, and Yu disclose forming the conformal oxide layer.
Hong in view of Mauder, Loose, and Yu does not disclose wherein the conformal oxide layer is formed by atomic layer deposition (ALD). However, Lee discloses techniques used to form a conformal oxide layer those processes being thermal oxidation, vapor deposition (e.g., chemical vapor position (CVD), plasma-enhanced chemical vapor deposition (PECVD), etc.), and/or layer deposition (e.g., atomic layer deposition (ALD), plasma-enhanced layer deposition (PLD), etc.). Forming an oxide layer with a conformal thickness over the fin (e.g., the channel) is generally a goal to pursue. The selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945). See MPEP 2144.07. Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to use an atomic layer deposition process and its corresponding materials to form the conformal oxide layer because it is suitable for forming a conformal oxide layer.
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20170345916 (Hong et al) in view of US 20180019132 (Mauder et al), US 20230164986 (Yu et al), and US 5747831 (Loose et al) as applied to claim 10 above, and further in view of US 20180374754 (Lee et al).
Pertaining to claim 11, Hong in view of Mauder, Yu, and Loose discloses forming the conformal oxide layer.
Hong in view of Mauder, Yu, and Loose does not disclose wherein the conformal oxide layer is formed by atomic layer deposition (ALD). However, Lee discloses techniques used to form a conformal oxide layer those processes being thermal oxidation, vapor deposition (e.g., chemical vapor position (CVD), plasma-enhanced chemical vapor deposition (PECVD), etc.), and/or layer deposition (e.g., atomic layer deposition (ALD), plasma-enhanced layer deposition (PLD), etc.). Forming an oxide layer with a conformal thickness over the fin (e.g., the channel) is generally a goal to pursue. The selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945). See MPEP 2144.07. Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to use an atomic layer deposition process and its corresponding materials to form the conformal oxide layer because it is suitable for forming a conformal oxide layer.
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20170345916 (Hong et al) in view of US 20180019132 (Mauder et al) and US 5747831 (Loose et al) as applied to claim 1 above, and further in view of US 20180374754 (Lee et al).
Pertaining to claim 7, Hong in view of Mauder and Loose discloses forming the top oxide cap.
Hong in view of Mauder and Loose does not disclose wherein the top oxide cap is formed by selective physical vapor deposition (PVD) of the top surface. However, Lee discloses techniques used to form an oxide layer those processes being thermal oxidation, vapor deposition (e.g., chemical vapor position (CVD), plasma-enhanced chemical vapor deposition (PECVD), etc.), and/or layer deposition (e.g., atomic layer deposition (ALD), plasma-enhanced layer deposition (PLD), etc.). Forming an oxide layer with a conformal thickness over the fin (e.g., the channel) is generally a goal to pursue. The selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945). See MPEP 2144.07. Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to use a selective physical vapor deposition (atomic layer deposition) process and its corresponding materials to form the oxide layer because it is suitable for forming an oxide layer.
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20130183804 (Wang et al) in view of US 20180019132 (Mauder et al) and US 5747831 (Loose et al) as applied to claim 16 above, and further in view of US 20180374754 (Lee et al).
As to claim 17, Wang in view of Mauder and Loose discloses forming the top oxide cap.
Wang in view of Mauder and Loose does not disclose wherein the top oxide cap is formed by selective physical vapor deposition (PVD) of the top surface. However, Lee discloses techniques used to form an oxide layer those processes being thermal oxidation, vapor deposition (e.g., chemical vapor position (CVD), plasma-enhanced chemical vapor deposition (PECVD), etc.), and/or layer deposition (e.g., atomic layer deposition (ALD), plasma-enhanced layer deposition (PLD), etc.). Forming an oxide layer with a conformal thickness over the fin (e.g., the channel) is generally a goal to pursue. The selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945). See MPEP 2144.07. Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to use a selective physical vapor deposition (atomic layer deposition) process and its corresponding materials to form the oxide layer because it is suitable for forming an oxide layer.
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20170345916 (Hong et al) in view of US 20180019132 (Mauder et al) and US 5747831 (Loose et al) as applied to claim 1 above, and further in view of US 20200035815 (Wu et al).
Concerning claim 9, Hong in view of Mauder and Loose discloses removing the top and bottom oxide (Mauder [0079]).
Hong in view of Mauder and Loose does not disclose wherein the top oxide cap and the bottom oxide cap are removed by a plasma etch. However, Wu discloses etching an oxide layer with several different processes/materials reactive ion etch (RIE), neutral beam etch (NBE), inductive coupled plasma (ICP) etch, or a combination thereof ([0027]). The selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945). See MPEP 2144.07. Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to use plasm etch process and its corresponding materials to remove the oxide layer because it is suitable for etching an oxide layer.
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20170345916 (Hong et al) in view of US 20180019132 (Mauder et al), US 20230164986 (Yu et al), and US 5747831 (Loose et al) as applied to claim 10 above, and further in view of US 20200035815 (Wu et al).
Concerning claim 15, Hong in view of Mauder, Yu and Loose discloses removing the top and bottom oxide (Mauder [0079]).
Hong in view of Mauder, Yu and Loose does not disclose wherein the top oxide cap and the bottom oxide cap are removed by a plasma etch. However, Wu discloses etching an oxide layer with several different processes/materials reactive ion etch (RIE), neutral beam etch (NBE), inductive coupled plasma (ICP) etch, or a combination thereof ([0027]). The selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945). See MPEP 2144.07. Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to use plasm etch process and its corresponding materials to remove the oxide layer because it is suitable for etching an oxide layer.
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20130183804 (Wang et al) in view of US 20180019132 (Mauder et al) and US 5747831 (Loose et al) as applied to claim 16 above, and further in view of US 20200035815 (Wu et al).
Continuing to claim 20, Wang in view of Mauder and Loose discloses removing the top and bottom oxide (Wang [0026] and Mauder [0076], note that the modified process of Wang in view of Mauder removes both the top and bottom oxide caps therefore the process in Wang that removes the top oxide cap is the same that removes the bottom oxide cap of the modified configuration of Wang in view of Mauder).
Wang in view of Mauder and Loose does not disclose wherein the top oxide cap and the bottom oxide cap are removed by a plasma etch. However, Wu discloses etching an oxide layer with several different processes/materials reactive ion etch (RIE), neutral beam etch (NBE), inductive coupled plasma (ICP) etch, or a combination thereof ([0027]). The selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945). See MPEP 2144.07. Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to use plasm etch process and its corresponding materials to remove the oxide layer because it is suitable for etching an oxide layer.
Response to Arguments
Applicant’s arguments, see pages 6-8, filed 07/09/26, with respect to the rejection(s) of claim(s) 1 under 102 and claims 10 and 16 under 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of US 5747831 (Loose et al).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VALERIE N NEWTON whose telephone number is (571)270-5015. The examiner can normally be reached M-F 8-5.
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/VALERIE N NEWTON/ Examiner, Art Unit 2897 09/17/26
/CHAD M DICKE/ Supervisory Patent Examiner, Art Unit 2897
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