DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Remarks
The amendment filed on June 29th, 2026 has been acknowledged. By this amendment, claims 1, 5, 7, 9-12, and 15-20 have been amended. Accordingly, claims 1-20 are pending in the present application in which claims 1, 12, and 17 are in independent form.
New Grounds of Rejection
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3, 6-12, and 14-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Brun et al. (U.S. Pub. 2023/0207475) in view of Shih (U.S. Pub. 2020/0203282), both of record, and Karikalan et al. (U.S. Pub. 2013/0168854), newly cited.
In re claim 1, Brun discloses a device 140 comprising: a first memory stack (150 on the left side of the device) comprising two or more memory dies (151,152,171) coupled to a substrate 148 (see paragraphs [0022], [0026], [0027] and fig. 1C); a second memory stack (150 on the right side of the device) comprising two or more memory dies (151,152,171) coupled to the substrate 148 (see paragraph [0027] and fig. 1C); a logic die (a first logic die 141 and a second logic die 142) electrically coupled to memory dies (150,152,171) of the first memory stack (150 on the left side of the device) to a top die 151 of the first memory stack and electrically coupled to memory dies (151,152,171) of the second memory stack (150 on the right side of the device) to a top die of the second memory stack (see paragraphs [0020], [0027] and fig. 1C, note that, active surface 153 of the first chiplet 151 facing the logic die 142); and a patch component 160 disposed in a region between the first memory stack (150 on the left side of the device) and the second memory stack (150 on the right side of the device), the package component 160 including a base material and conductors 161 that extend through the base material (see paragraphs [0020], [0021] and fig. 1C) and electrically couple the logic die (141 or 142) to the substrate 148 (see paragraph [0021] and fig. 1C).
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Brun discloses that there is a first logic die 141 and a second logic die 142 for electrically connected to the first memory stack (150 on the left side of the device) and the second memory stack (150 on the right side of the device) (see paragraphs [0020], [0022] and fig. 1C). However, Brun is silent to a logic die electrically connected to memory dies of the first memory stack through face-to-face connections to a top die of the first memory stack and electrically connected to memory dies of the second memory stack through face-to-face connections to a top die of the second memory stack.
However, Shih discloses in a same field of endeavor, a device, including, inter-alia, a logic die 210 (see paragraph [0037] and fig. 8, note that, the logic die 210 includes any one of APU, CPU, GPU, microprocessors, ASICs, DSPs, or the like) electrically connected to a first memory die 220 (on the left side of the device) and a second memory die 220 (on the right side of the device) through face-to-face connection (see paragraphs [0038], [0040] and fig. 8).
Therefore, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to be motivated to incorporate the technique as taught by Shih into the device of Brun in order to enable a logic die electrically connected to memory dies of the first memory stack through face-to-face connections to a top die of the first memory stack and electrically connected to memory dies of the second memory stack through face-to-face connections to a top die of the second memory stack in Brun to be formed in order to increase in memory capacity, improve mounting density, and improve mounting area utilization efficiency. Furthermore, it would have been obvious because all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination would have yielded predictable results to one of ordinary skill in the art at the time of the invention. KSR International Co. v. Teleflex Inc. (KSR), 550 U.S. 398 (2007). “If a technique has been used to improve one device, and a person of ordinary skill in the art would recognize that it would improve similar devices in the same way, using the technique is obvious unless its actual application is beyond that person’s skill.” Id.
Brun and Shih discloses wherein the device comprises the patch component 160 including TSVs 161 that electrically couple the logic die (141,142) to the substrate 148 (see paragraphs [0021], [0025] and fig. 1C of Brun) but are silent to wherein the patch component including a polymer-based material and conductors that extend through the polymer-based material and electrically couple the logic die to the substrate.
However, Karikalan discloses in a same field of endeavor, a device including, inter-alia, a patch component 130 including a polymer-based material 132 (see paragraphs [0013], [0014], [0015] and figs. 1A-C) and conductors 134 that extend through the polymer-based material 132 and electrically couple the logic die (110,120) to the substrate 102 (see paragraphs [0013], [0014], [0015] and figs. 1A-C).
Therefore, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to be motivated to incorporate the technique as taught by Karikalan into the device of Brun in order to enable wherein the patch component including a polymer-based material and conductors that extend through the polymer-based material and electrically couple the logic die to the substrate in Brun to be formed in order to prevent leakage through the substrate resulting from parasitic coupling amongst the TSVs that would adversely affect electrical signals passing through the patch component (see paragraph [0002] of Karikalan). Furthermore, it would have been obvious because all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination would have yielded predictable results to one of ordinary skill in the art at the time of the invention. KSR International Co. v. Teleflex Inc. (KSR), 550 U.S. 398 (2007). “If a technique has been used to improve one device, and a person of ordinary skill in the art would recognize that it would improve similar devices in the same way, using the technique is obvious unless its actual application is beyond that person’s skill.” Id.
In re claim 3, as applied to claim 1 above, Brun in combination with Shih and Karikalan discloses wherein the top die 151 of the first memory stack (150 on the left side of the device) comprises a memory controller for the two or more memory dies (152,171) of the first memory stack (see paragraph [0022] and fig. 1C of Brun).
In re claim 6, as applied to claim 1 above, Brun in combination with Shih and Karikalan discloses wherein a body of the patch component 160 comprises a core layer, and wherein the conductors comprise vias 161 extending through the core layer (see paragraph [0021] and fig. 1C of Brun).
In re claim 7, as applied to claim 1 above, Brun in combination with Shih and Karikalan discloses wherein a body of the patch component comprises a first layer of a semiconductor layer 451 stacked on a second layer 476 including the polymer-based material, and wherein one or more of the conductors comprises a through silicon via 459 extending through the semiconductor layer 451 (see paragraphs [0042], [0043] and fig. 4F of Brun).
In re claim 8, as applied to claim 1 above, Brun in combination with Shih and Karikalan discloses wherein the patch component 160 includes active circuit components, passive circuit components, or both (see paragraph [0021] and fig. 1C of Brun).
In re claim 9, as applied to claim 1 above, Brun and Karikalan are silent to wherein the device further comprising: one or more additional memory stacks comprising two or more memory dies coupled to the substrate; and a second logic die electrically coupled to memory dies of the one or more additional memory stacks through face-to-face connections to a top die of each of the one or more additional memory stacks, wherein the conductors of the patch component electrically coupled the second logic die to the substrate.
However, Shih discloses wherein the device further comprising one or more additional memory stack (on the right side of the device) comprises two or more memory dies 220 coupled to the substrate 201 and a second logic die (210 on the right side of the device) electrically coupled to the memory dies 220 of the one or more additional memory stack through face-to-face connections to a top die of each of the one or more additional memory stack, wherein the conductors of the patch component electrically couple the second logic die 210 to the substrate 201 (see paragraph [0046] and fig. 8).
Therefore, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to be motivated to incorporate the technique as taught by Shih into the device of Brun in order to enable wherein the device further comprising: one or more additional memory stacks comprising two or more memory dies coupled to the substrate; and a second logic die electrically couple to memory dies of the one or more additional memory stacks through face-to-face connections to a top die of each of the one or more additional memory stacks, wherein the conductors of the patch component electrically couple the second logic die to the substrate in Brun to be formed in order to improve functionality of the memory device.
In re claim 10, as applied to claim 9 above, Brun in combination with Shih and Karikalan discloses wherein the device further comprising redistribution layers between the logic die and the first memory stack, between the logic die and the second memory stack, between the second logic die and the one or more additional memory stacks, and electrically coupling the logic die to the second logic die (see paragraph [0046] and fig. 8 of Shih).
In re claim 11, as applied to claim 9 above, Brun in combination with Shih and Karikalan discloses wherein the logic die is electrically coupled to the second logic die through the patch component 232 (see paragraph [0045] and fig. 8 of Shih).
In re claim 12, Brun discloses a device comprising: a first memory stack (150 on the left side of the device) comprising two or more memory dies (151,152,171) coupled to a substrate 148 (see paragraph [0027] and fig. 1C); a second memory stack (150 on the right side of the device) comprising two or more memory dies (151,152,171) coupled to the substrate 148 (see paragraph [0027] and fig. 1C); a first logic die 141 electrically coupled to memory dies (151,152,171) of the first memory stack (150 on the right side of the device) to a top die 151 of the first memory stack (see paragraphs [0020], [0022] and fig. 1C); a second logic die 142 electrically coupled to memory dies (151,152,171) of the second memory stack (150 on the right side of the device) to a top die 151 of the second memory stack (see paragraphs [0020], [0022] and fig. 1C); and a patch component 160 disposed in a region between the first memory stack (150 on the left side of the device) and the second memory stack (150 on the right side of the device), the patch component 160 including a base material, first conductors 161 extend through the base material and electrically couple the first logic die 141 to the substrate 148 and second conductors 161 that electrically couplet the second logic die 142 to the substrate 148 (see paragraph [0021] and fig. 1C).
Brun is silent to wherein a first logic die electrically connected to memory dies of the first memory stack through face-to-face connections to a top die of the first memory stack; a second logic die electrically connected to memory dies of the second memory stack through face-to-face connections to a top die of the second memory stack.
However, Shih discloses in a same field of endeavor, a device, including, inter-alia, a first logic die 210 (on the left side of the device) (see paragraph [0037] and fig. 8, note that, the logic die 210 includes any one of APU, CPU, GPU, microprocessors, ASICs, DSPs, or the like) electrically connected to a first memory die 220 (on the left side of the device) through face-to-face connection (see paragraphs [0038], [0040] and fig. 8) and a second logic die 210 (on the right side of the device) electrically connected to the second memory die 220 (on the right side of the device) through face-to-face connections (see paragraph [0038], [0040] and fig. 8).
Therefore, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to be motivated to incorporate the technique as taught by Shih into the device of Brun in order to enable wherein a first logic die electrically connected to memory dies of the first memory stack through face-to-face connections to a top die of the first memory stack; a second logic die electrically connected to memory dies of the second memory stack through face-to-face connections to a top die of the second memory stack in Brun to be formed in order to increase in memory capacity, improve mounting density, and improve mounting area utilization efficiency. Furthermore, it would have been obvious because all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination would have yielded predictable results to one of ordinary skill in the art at the time of the invention. KSR International Co. v. Teleflex Inc. (KSR), 550 U.S. 398 (2007). “If a technique has been used to improve one device, and a person of ordinary skill in the art would recognize that it would improve similar devices in the same way, using the technique is obvious unless its actual application is beyond that person’s skill.” Id.
Brun and Shih discloses wherein the device comprises the patch component 160 including TSVs 161 that electrically couple the logic die (141,142) to the substrate 148 (see paragraphs [0021], [0025] and fig. 1C of Brun) but are silent to wherein the patch component including a polymer-based material, first conductors that extend through the polymer-based material and electrically couple the first logic die to the substrate, and second conductors that electrically couple the second logic die to the substrate.
However, Karikalan discloses in a same field of endeavor, a device including, inter-alia, a patch component 130 including a polymer-based material 132 (see paragraphs [0013], [0014], [0015] and figs. 1A-C), first conductors 134 that extend through the polymer-based material 132 and electrically couple the first logic die 110 to the substrate 102, and second conductors (adjacent 134) that electrically couple the second logic die 120 to the substrate (see paragraphs [0013], [0014], [0015] and figs. 1A-C).
Therefore, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to be motivated to incorporate the technique as taught by Karikalan into the device of Brun in order to enable wherein the patch component including a polymer-based material, first conductors that extend through the polymer-based material and electrically couple the first logic die to the substrate, and second conductors that electrically couple the second logic die to the substrate in Brun to be formed in order to prevent leakage through the substrate resulting from parasitic coupling amongst the TSVs that would adversely affect electrical signals passing through the patch component (see paragraph [0002] of Karikalan). Furthermore, it would have been obvious because all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination would have yielded predictable results to one of ordinary skill in the art at the time of the invention. KSR International Co. v. Teleflex Inc. (KSR), 550 U.S. 398 (2007). “If a technique has been used to improve one device, and a person of ordinary skill in the art would recognize that it would improve similar devices in the same way, using the technique is obvious unless its actual application is beyond that person’s skill.” Id.
In re claim 14, as applied to claim 12 above, Brun in combination with Shih and Karikalan discloses wherein the top die 151 of the first memory stack 150 (on the right side of the device) comprises a first memory controller for the two or more memory dies (152,171) of the first memory stack, and the top die 151 of the second memory stack 150 (on the right side of the device) comprises a second memory controller for the two or more memory dies (152,171) of the second memory stack (see paragraph [0022] and fig. 1C of Brun).
In re claim 15, as applied to claim 12 above, Brun in combination with Shih and Karikalan discloses wherein the first logic die 141 and the second logic die 142 are electrically coupled to one another through the patch component 160 (see paragraph [0021] and fig. 1C of Brun).
In re claim 16, as applied to claim 12 above, Brun in combination with Shih and Karikalan discloses wherein the device further comprising redistribution layers 146 disposed between the first logic die 141 and the first memory stack 150 (on the left side of the device), between the second logic die 142 and the second memory stack (150 on the right side of the device), and electrically coupling the first logic die 141 to the second logic die 142 (see paragraph [0020] and fig. 1C of Brun).
In re claim 17, Brun discloses a method comprising: coupling a plurality of memory stacks 150 to a substrate 148, each memory stack comprising two or more memory dies (151,152,171) (see paragraphs [002], [[0027] and fig. 1C); electrically coupling a patch component 160 to the substrate 148 in a region between two or more memory stacks 150 of the plurality of memory stacks (see paragraph [0021] and fig. 1C), the patch component 160 including a base material and conductors 161 (TSVs) extend through the base material (see paragraphs [0020], [0021] and fig. 1C); and electrically coupling a logic die (141 or 142) to the substrate 148 via the conductors of the patch component 160, and to top dies 151 of the two or more memory stacks 150 (see paragraph [0022] and fig. 1C).
Brun is silent to electrically connecting the logic die through face-to-face to top dies of the two or more memory stacks.
However, Shih discloses in a same field of endeavor, a method for manufacturing a device, including, inter-alia, a logic die 210 (see paragraph [0037] and fig. 8, note that, the logic die 210 includes any one of APU, CPU, GPU, microprocessors, ASICs, DSPs, or the like) electrically connected to a first memory die 220 (on the left side of the device) and a second memory die 220 (on the right side of the device) through face-to-face connection (see paragraphs [0038], [0040] and fig. 8).
Therefore, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to be motivated to incorporate the technique as taught by Shih into the device of Brun in order to enable the process of electrically connecting the logic die through face-to-face to top dies of the two or more memory stacks in Brun to be performed in order to increase in memory capacity, improve mounting density, and improve mounting area utilization efficiency. Furthermore, it would have been obvious because all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination would have yielded predictable results to one of ordinary skill in the art at the time of the invention. KSR International Co. v. Teleflex Inc. (KSR), 550 U.S. 398 (2007). “If a technique has been used to improve one device, and a person of ordinary skill in the art would recognize that it would improve similar devices in the same way, using the technique is obvious unless its actual application is beyond that person’s skill.” Id.
Brun and Shih discloses wherein the device comprises the patch component 160 including TSVs 161 that electrically couple the logic die (141,142) to the substrate 148 (see paragraphs [0021], [0025] and fig. 1C of Brun) but are silent to wherein the patch component including a polymer-based material and conductors extend through the polymer-based material and electrically coupling the logic die to the substrate via the conductors of the patch component.
However, Karikalan discloses in a same field of endeavor, a device including, inter-alia, a patch component 130 including a polymer-based material 132 (see paragraphs [0013], [0014], [0015] and figs. 1A-C) and conductors 134 extend through the polymer-based material 132 and electrically coupling the logic die (110,120) to the substrate 102 via the conductors 134 of the patch component 130 (see paragraphs [0013], [0014], [0015] and figs. 1A-C).
Therefore, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to be motivated to incorporate the technique as taught by Karikalan into the device of Brun in order to enable wherein the patch component including a polymer-based material and conductors extend through the polymer-based material and electrically coupling the logic die to the substrate via the conductors of the patch component in Brun to be formed in order to prevent leakage through the substrate resulting from parasitic coupling amongst the TSVs that would adversely affect electrical signals passing through the patch component (see paragraph [0002] of Karikalan). Furthermore, it would have been obvious because all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination would have yielded predictable results to one of ordinary skill in the art at the time of the invention. KSR International Co. v. Teleflex Inc. (KSR), 550 U.S. 398 (2007). “If a technique has been used to improve one device, and a person of ordinary skill in the art would recognize that it would improve similar devices in the same way, using the technique is obvious unless its actual application is beyond that person’s skill.” Id.
In re claim 18, as applied to claim 17 above, Brun in combination with Shih and Karikalan discloses wherein the method further comprising electrically coupling a second logic die 142 to the substrate 148 through the patch component 160 to top dies of two or more additional memory stacks 150 of the plurality of memory stacks (see paragraphs [0021], [0022] and fig. 1C of Brun).
Brun is silent to electrically connecting the second logic die to the substrate through face-to-face to top dies of two or more additional memory stacks of the plurality of memory stacks.
However, Shih discloses in a same field of endeavor, a method for manufacturing a device, including, inter-alia, a logic die 210 (see paragraph [0037] and fig. 8, note that, the logic die 210 includes any one of APU, CPU, GPU, microprocessors, ASICs, DSPs, or the like) electrically connected to a first memory die 220 (on the left side of the device) and a second memory die 220 (on the right side of the device) through face-to-face connection (see paragraphs [0038], [0040] and fig. 8).
Therefore, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to be motivated to incorporate the technique as taught by Shih into the device of Brun in order to enable the process of electrically connecting the second logic die to the substrate through face-to-face to top dies of two or more additional memory stacks of the plurality of memory stacks in Brun to be performed in order to increase in memory capacity, improve mounting density, and improve mounting area utilization efficiency. Furthermore, it would have been obvious because all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination would have yielded predictable results to one of ordinary skill in the art at the time of the invention. KSR International Co. v. Teleflex Inc. (KSR), 550 U.S. 398 (2007). “If a technique has been used to improve one device, and a person of ordinary skill in the art would recognize that it would improve similar devices in the same way, using the technique is obvious unless its actual application is beyond that person’s skill.” Id.
In re claim 19, as applied to claim 18 above, Brun in combination with Shih and Karikalan discloses wherein the method further comprising electrically coupling the logic die 141 to the second logic die 142 through the patch component. 160 (see paragraph [0021] and fig. 1C of Brun).
In re claim 20, as applied to claim 18 above, Brun in combination with Shih and Karikalan discloses wherein the method further comprising electrically coupling the logic die 141 to the second logic die 142 through redistribution layers 146 (see paragraph [0020] and fig. 1C of Brun).
Claim(s) 2 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Brun et al. (U.S. Pub. 2023/0207475) in view of Shih (U.S. Pub. 2020/0203282), both of record, and Karikalan et al. (U.S. Pub. 2013/0168854), newly cited, as applied to claims 1 and 12 above, respectively, and further in view of Ku et al. (U.S. Pub. 2019/0385929), of record.
In re claim 2, as applied to claim 1 above, Brunm Shih, and Karikalan are silent to wherein the first memory stack comprises a high bandwidth memory (HBM) stack
However, Ku discloses in a same field of endeavor, a device, including inter-alia, a first memory stack 117 comprising a high bandwidth memory (HBM) stack (see paragraph [0026] and fig. 1A).
Therefore, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to be motivated to incorporate the technique as taught by Ku into the device of Brun in order to enable wherein the first memory stack comprises a high bandwidth memory (HBM) stack in Brun to be formed in order to obtain a 3D-IC module.
In re claim 13, as applied to claim 12 above, Brun, Shih, and Karikalan are silent wherein the first memory stack comprises a first high bandwidth memory stack and the second memory stack comprises a second high bandwidth memory stack.
However, Ku discloses in a same field of endeavor, a device, including inter-alia, a first memory stack 117 (on the left side of the device) comprising a high bandwidth memory (HBM) stack and a second memory stack 117 (on the right side of the device) comprises a second high bandwidth memory stack (see paragraph [0026] and fig. 1A).
Therefore, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to be motivated to incorporate the technique as taught by Ku into the device of Brun in order to enable wherein the first memory stack comprises a first high bandwidth memory stack and the second memory stack comprises a second high bandwidth memory stack in Brun to be formed in order to obtain a 3D-IC module.
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Brun et al. (U.S. Pub. 2023/0207475) in view of Shih (U.S. Pub. 2020/0203282), both of record, and Karikalan et al. (U.S. Pub. 2013/0168854), newly cited, as applied to claim 1 above, and further in view of Jung et al. (U.S. Pub. 2022/0262780), of record.
In re claim 4, as applied to claim 1 above, Brun is silent to wherein a body of the patch component comprises mold compound, and wherein the conductors comprise through mold vias extending through the mold compound.
However, Jung discloses in a same field of endeavor, a device, including, inter-alia, a body of the patch component comprises mold compound, and wherein the conductors comprise through mold vias 137 extending through the mold compound 135 (see paragraph [0045] and fig. 2).
Therefore, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to be motivated to incorporate the technique as taught by Jung into the device of Brun in order to enable wherein a body of the patch component comprises mold compound, and wherein the conductors comprise through mold vias extending through the mold compound in Brun to be formed in order to improve the performance of the memory device (see paragraph [0033] of Jung).
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Brun et al. (U.S. Pub. 2023/0207475) in view of Shih (U.S. Pub. 2020/0203282), both of record, and Karikalan et al. (U.S. Pub. 2013/0168854), newly cited, as applied to claim 1 above, and further in view of Wei et al. (U.S. Pub. 2022/0278115), of record.
In re claim 5, as applied to claim 1 above, Brun, Shih, and Karikalan are silent to wherein a body of the patch component comprises a multilayer structure, and wherein the conductors comprise stacked and electrically connected conductors extending through layers of the multilayer structure.
However, Wei discloses in a same field of endeavor, a device, including, inter-alia, wherein a body of the patch component comprises a multilayer structure (MLI), and wherein the conductors comprise stacked and electrically connected conductors extending through layers of the multilayer structure (see paragraph [0036]).
Therefore, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to be motivated to incorporate the technique as taught by Wei into the device of Brun in order to enable wherein a body of the patch component comprises a multilayer structure, and wherein the conductors comprise stacked and electrically connected conductors extending through layers of the multilayer structure in Brun to be formed in order to improve performance of the memory device.
Response to Applicant’s Amendment and Arguments
Applicant’s arguments with respect to claim(s) 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/KHIEM D NGUYEN/Primary Examiner, Art Unit 2892
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