DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 02/01/2024. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 10-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In Claim 10, the recitation of “a second transistor of a second polarity type and having a control terminal coupled to the third terminal and having a control terminal and first and second terminals” it is not clear which control terminal is the applicant referring to, it is noted the second transistor appear discloses three terminals transistor. Further clarification is needed.
Claim 16 is rejected in the same manner as discussed in claim 10.
Claims 11-15 are rejected due to their dependency. Claims 17-20 are rejected due to their dependency.
For the purpose examining, the examiner read “having a control terminal and first and second terminals” as ----having first and second terminals---.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3, 10-11 & 15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shacter (US 5,847,606 A).
Regarding claim 1:
Shacter discloses in Figs. 2-4 an amplifier comprising:
a first transistor (M2, NMOS) of a first polarity type (n-type) and having a control terminal (gate) and first and second terminals;
a second transistor (M6, PMOS) of a second polarity type (p-type) and having a control terminal (gate) and first and second terminals;
a third transistor (M3, NMOS) of the first polarity type (n-type) and having a control terminal (gate) and first and second terminals,
the second terminal (drain of M3) of the third transistor (M3) coupled to the first terminal (drain) of the second transistor (M6);
a fourth transistor (M7, PMOS) of the second polarity type (p-type) and having a control terminal (gate) and first and second terminals, the first terminal (source) of the fourth transistor (M7) coupled to the second terminal (source) of the second transistor (M6);
a fifth transistor (M4, NMOS) having a control terminal (gate) coupled to the control terminal (gate) of the third transistor (M3); and
a sixth transistor (M8, PMOS) having a control terminal (gate) coupled to the control terminal (gate) of the fourth transistor (M7).
Regarding claim 3:
Shacter discloses in Figs. 2-4, the amplifier of claim 1, wherein the fifth transistor is of the first polarity type (n-type), and the sixth transistor is of the second polarity type (p-type).
Regarding claim 10 as best understood:
Shacter discloses in Fig. 4 an amplifier, comprising:
an input stage circuit (includes transistors M31 & M32) having first (vinpos, vinneg) and second terminals (drain terminals of transistor M35, M36) ;
a voltage gain circuit (circuit includes transistors M24, M25, M29, M30, M37-M40) having a first terminal (a terminal between transistor M24 and M29) coupled to the first terminal (drain terminal of transistor M35) of the input stage circuit and having a second terminal (a terminal between transistors M25 and M30) coupled to the second terminal (drain terminal of M36) of the input stage circuit, the voltage gain circuit having a third terminal (e.g., drain terminal of transistor M30);
a first transistor (M2) of a first polarity type (n-type) and having a control terminal coupled to the third terminal and having first and second terminals;
a second transistor (M6) of a second polarity type (p-type) and having a control terminal coupled to the third terminal and having
a third transistor (M3) of the first polarity type (n-type) and having a control terminal and first and second terminals, the second terminal (drain) of the third transistor (M3) coupled to the first terminal (drain) of the second transistor (M6);
a fourth transistor (M7) of the second polarity type (p-type) and having a control terminal and first and second terminals, the first terminal (source) of the fourth transistor (M7) coupled to the second terminal (source) of the second transistor (M6);
a fifth transistor (M4) having a control terminal coupled to the control terminal of the third transistor (M3); and
a sixth transistor (M8) having a control terminal coupled to the control terminal of the fourth transistor (M7).
Regarding claim 11:
Shacter discloses in Fig. 4, the amplifier of claim 10, wherein the input stage circuit includes a transconductance circuit (includes transistor M31, M32).
Regarding claim 15:
Shacter discloses in Fig. 4, the amplifier of claim 10, wherein the first, second, third, and fourth transistors are field effect transistors (as shown in Fig. 4, PMOS and NMOS transistors).
Claims 1, 3, 5 & 16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Damitio et al. (US 20120146725 A, hereinafter Damitio).
Regarding claim 1:
Damitio discloses in Fig. 4 an amplifier comprising:
a first transistor (Q42) of a first polarity type (n-type) and having a control terminal (base) and first and second terminals;
a second transistor (Q18) of a second polarity type (p-type) and having a control terminal (base) and first and second terminals;
a third transistor (Q3) of the first polarity type (n-type) and having a control terminal (gate) and first and second terminals,
the second terminal (collector of Q3) of the third transistor (Q3) coupled to the first terminal (collector of Q18) of the second transistor (Q18);
a fourth transistor (Q16) of the second polarity type (p-type) and having a control terminal (base) and first and second terminals, the first terminal (emitter) of the fourth transistor (Q16) coupled to the second terminal (emitter) of the second transistor (Q18);
a fifth transistor (Q4) having a control terminal (base) coupled to the control terminal (base) of the third transistor (Q3); and
a sixth transistor (Q17) having a control terminal (base) coupled to the control terminal (base) of the fourth transistor (Q16).
Regarding claim 3:
Damitio discloses in Fig. 4, the amplifier of claim 1, wherein the fifth transistor is of the first polarity type (n-type), and the sixth transistor is of the second polarity type (p-type).
Regarding claim 5:
Damitio discloses in Fig. 4, the amplifier of claim 1, wherein the first, second, third, fourth, fifth, and sixth transistors are bipolar junction transistors, the first polarity type is NPN, and the second polarity type is PNP.
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Regarding claim 16:
Damitio discloses in Fig. 4, an amplifier, comprising:
base-connected bipolar junction transistors (BJTs) of different polarity types (bipolar transistor, n-type and p-type), the base-connected BJTs having a first terminal (annotated terminal A)and a second terminal (annotated terminal B);
a first transistor (Q42) of a first polarity type (n-type) and having a control terminal (base) coupled to the first terminal (terminal A) of the base-connected BJTs, and having first and second terminals;
a second transistor (Q16) of a second polarity type (p-type) and having a control terminal coupled to the second terminal (terminal B) of the base-connected BJTs, and having
a third transistor (Q3) of the first polarity type (n-type) and having a control terminal (base) and first and second terminals, the second terminal (collector) of the third transistor (Q3) coupled to the first terminal (collector of Q18) of the second transistor (Q18);
a fourth transistor (Q16) of the second polarity type (p-type) and having a control terminal (base) and first and second terminals, the first terminal (emitter) of the fourth transistor (Q16) coupled to the second terminal (emitter) of the second transistor (Q18); a fifth transistor(Q4) having a control terminal (base) coupled to the control terminal of the third transistor (Q3); and a
sixth transistor (Q17) having a control terminal (base) coupled to the control terminal of the fourth transistor (Q16).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Shacter or Damitio.
Regarding claim 4:
Shacter discloses the limitations as applied in claim 1 except for wherein the first transistor is smaller than the third transistor, and the third transistor is smaller than the second transistor. It would have been obvious to one having ordinary skill in the art at the time the invention was made to have chosen the first transistor is smaller than the third transistor, and the third transistor is smaller than the second transistor, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617F.2d 272, 205 USPQ 215 (CCPA 1980).
Allowable Subject Matter
Claims 2 & 6-9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 2 is allowable since the closest prior art (i.e. Shacter) does not disclose wherein the fifth transistor is of the second polarity type (p-type), and the sixth transistor is of the first polarity type (n-type).
Claims 6 & 7 are allowable since the closest prior art (i.e. Shacter) does not disclose further comprising: a transconductance circuit having an input and an output; and a voltage gain circuit having an input and an output, the input of the voltage gain circuit coupled to the output of the transconductance circuit, and the output of the voltage gain circuit coupled to the control terminals of first and second transistors.
Claims 8 & 9 are allowable since the closest prior art (i.e. Shacter) does not disclose further comprising a third current source circuit coupled between the first supply voltage terminal and the first terminal of the third transistor; and a fourth current source circuit coupled between the second supply voltage terminal and the second terminal of the fourth transistor.
Claims 12-14 & 17-20 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHIEM D NGUYEN whose telephone number is (571)270-3941. The examiner can normally be reached Mon-Fri 8:00 AM-5:00 PM EST.
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/KHIEM D NGUYEN/Examiner, Art Unit 2843
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