DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Response to Arguments
Applicant’s reply filed on 12/19/2025 has been entered and considered. Applicant’s amendments necessitated the shift in grounds of rejection detailed below. The shift in grounds of rejection renders Applicant’s arguments moot. Thus, this rejection is properly made FINAL.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-11 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Regarding Claim 1, The instant claims recite limitation “a platinum containing layer connected to a first lateral side of the first platinum silicide layer and connected to a second lateral side of the second platinum silicide layer” is not clear because platinum containing layer 220 (as shown in figure 2) appears connected either a first lateral side of the first platinum silicide layer or a second lateral side of the second platinum silicide layer. Platinum containing layer is not connected both lateral end of first platinum silicide layer and the second platinum silicide layer. Therefore, the resulting claim is indefinite and is failing to particularly point out and distinctly claim the subject matter. For the purpose of examination, examiner interpreted, platinum containing layer disposed on the first and second platinum silicide layer. Appropriate corrections defining these limitations within metes and bounds of the claimed invention are required.
Claims 2-11 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, because of their dependency status from claim 1.
Claim Rejection- 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 8-11 is rejected under 35 U.S.C. 103 as being unpatentable over HAYASHI et al (US 2009/0149020 A1; hereafter HAYASHI) in view of Williams et al (US 2007/0278612 A1; hereafter Williams).
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Regarding claim 1. HAYASH discloses a semiconductor device, comprising:
a first transistor (Fig. [5], transistor 10n, Para [ 0051]) in a substrate (Fig. [5], substrate 1, Para [ 0048]), the first transistor including:
a first doped region (Fig. [5], source/drain diffusion region 16, Para [ 0053]) extended into the substrate (Fig. [5], substrate 1, Para [ 0048]); and
a first platinum silicide layer (Fig. [5], platinum silicide layer 18, Para [ 0054]) disposed on the first doped region (Fig. [5], source/drain diffusion region 16, Para [ 0053]);
a second transistor (Fig. [5], transistor 10p, Para [ 0051]) in the substrate (Fig. [5], substrate 1, Para [ 0048]), the second transistor (Fig. [5], transistor 10p, Para [ 0051]) including:
a second doped region (Fig. [5], source/drain diffusion region 17, Para [ 0053]) extended into the substrate (Fig. [5], substrate 1, Para [ 0048]); and
a second platinum silicide layer (Fig. [5], platinum silicide layer 18, Para [ 0054]) disposed on the second doped region (Fig. [5], source/drain diffusion region 17, Para [ 0053]); and
a metal containing layer (barrier metal 21, made with tungsten Para [ 0058]) connected to a first side of the first platinum silicide layer (Fig. [5], platinum silicide layer 18, Para [ 0054]) and connected to a second side of the second platinum silicide layer (Fig. [5], platinum silicide layer 18, Para [ 0054]).
But HAYASHI does not disclose explicitly barrier metal film made with platinum.
In a similar field of endeavor, Williams discloses barrier metal film made with platinum (Para [0011] discloses barrier metal typically comprising titanium, platinum or tungsten).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine HAYASHI in light of Williams teaching “barrier metal film made with platinum (Para [0011] discloses barrier metal typically comprising titanium, platinum or tungsten)” for further advantage such as to prevent metal spikes (i.e. filaments) from alloying through the N+ to P-well junction during processing and shorting out the transistor's junctions ( Williams Para [ 0011]).
Regarding claim 8. HAYASHI in light of Williams discloses the semiconductor device of claim 1, HAYASHI further discloses further comprising:
an isolation structure (Fig. [5], isolation region 4, Para [ 0048]) disposed between the first doped region (Fig. [5], source/drain diffusion region 16, Para [ 0053]) and the second doped region (Fig. [5], source/drain diffusion region 17, Para [ 0053]), wherein the metal containing layer (barrier metal 21, made with tungsten Para [ 0058]) is on the isolation structure (Fig. [5], isolation region 4, Para [ 0048]).
But HAYASHI does not disclose explicitly barrier metal film made with platinum.
In a similar field of endeavor, Williams discloses barrier metal film made with platinum (Para [0011] discloses barrier metal typically comprising titanium, platinum or tungsten).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Lee in light of Williams teaching “barrier metal film made with platinum (Para [0011] discloses barrier metal typically comprising titanium, platinum or tungsten)” for further advantage such as to prevent metal spikes (i.e. filaments) from alloying through the N+ to P-well junction during processing and shorting out the transistor's junctions ( Williams Para [ 0011]).
Regarding claim 9. HAYASHI in light of Williams discloses the semiconductor device of claim 1, HAYASHI further discloses wherein: the first doped region (Fig. [5], source/drain diffusion region 16, Para [ 0053]) is a first conductivity type (Para [ 0053]); and the second doped region is a second conductivity type (Fig. [5], source/drain diffusion region 17, Para [ 0053]) opposite the first conductivity type (Para [ 0053]).
Regarding claim 10. HAYASHI in light of Williams discloses the semiconductor device of claim 1, HAYASHI further discloses wherein: the first doped region (Fig. [5], source/drain diffusion region 16, Para [ 0053]) is located in a third doped region (p-type well 6, Para [ 0049]) of the substrate (Fig. [5], substrate 1, Para [ 0048]), the third doped region (p-type well 6, Para [ 0049]) having a conductivity type opposite the first doped region (Fig. [5], source/drain diffusion region 16, Para [ 0053]); and the second doped region (Fig. [5], source/drain diffusion region 17, Para [ 0053]) is located in a fourth doped region (n-type well 8, Para [ 0049]) of the substrate (Fig. [5], substrate 1, Para [ 0048]), the fourth doped region (n-type well 8, Para [ 0049]) having a conductivity type opposite the second doped region (Fig. [5], source/drain diffusion region 17, Para [ 0053]).
Regarding claim 11. HAYASHI in light of Williams discloses the semiconductor device of claim 1, HAYASHI further discloses wherein: the first doped region is a source or a drain region (Fig. [5], source/drain diffusion region 16, Para [ 0053]) of the first transistor (Fig. [5], transistor 10n, Para [ 0051]); and the second doped region is a source or a drain region (Fig. [5], source/drain diffusion region 17, Para [ 0053]) of the second transistor (Fig. [5], transistor 10p, Para [ 0051]).
Claims 12 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Son et al (US 2006/0027848 A1; hereafter Son) in view of Tseng et al (US 2013/0193577 A1; hereafter Tseng).
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Regarding claim 12. Son discloses a semiconductor device, comprising:
a first transistor (Fig. [1], left transistor, Para [ 0015, 0021-0026]) in a substrate (Fig. [1], substrate 1, Para [ 0021]), the first transistor including a first doped region (Fig. [1], left doped region 7, Para [ 0021]) extended into the substrate (Fig. [1], substrate 1, Para [ 0021]);
a second transistor in the substrate (Fig. [1], right transistor, Para [ 0015, 0021-0026]), the second transistor including a second doped region (right doped region 7, Para [ 0021]) extended into the substrate (Fig. [1], substrate 1, Para [ 0021]); and
a local interconnect (Fig. [1], diffusion layer/ lower electrode [19, 21], Para [ 0021-0027], construed as local interconnect) electrically coupling the first doped region (left doped region 7, Para [ 0021]) to the second doped region (right doped region 7, Para [ 0021]), wherein the local interconnect includes a metal layer (Fig. [1], diffusion layer 19, Para [ 0021-0026]) and a platinum oxide layer directly (Fig. [1], lower electrode 21, Para [ 0022]) on the metal layer (Fig. [1], lower electrode [21], made with platinum oxide, Para [ 0021-0027]).
But Son does not disclose explicitly metal layer made with platinum.
In a similar field of endeavor, Tseng discloses metal layer made with platinum (Fig 9, metal layer 160, Para [ 0025]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Son in light of Tseng teaching “metal layer made with platinum (Fig 9, metal layer 160, Para [ 0025])” for further advantage such as to enhance electrical connectivity of the semiconductor device.
Regarding claim 20. Son and Tseng discloses the semiconductor device of claim 12, Son further discloses wherein: the first doped region is a source or a drain region (left doped region 7, Para [ 0015, 0021]) of the first transistor (Fig. [7], left transistor, Para [ 0015,0021-0026]); and the second doped region is a source or a drain region (right doped region 7, Para [ 0015, 0021]) of the second transistor (Fig. [7], right transistor, Para [ 0015, 0021-0026]).
Claims 13 and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Son et al (US 2006/0027848 A1; hereafter Son) in view of Tseng et al (US 2013/0193577 A1; hereafter Tseng) as applied claims above and further in view of HAYASHI et al (US 2009/0149020 A1; hereafter HAYASHI).
Regarding claim 13. Son and Tseng disclose the semiconductor device of claim 12, Song further discloses further comprising:
a first layer (left contact 9, Para [ 0021-0022]) disposed on the first doped region (left doped region 7, Para [ 0015, 0021]); and
a second layer (right contact 9, Para [ 0021-0022]) disposed on the second doped region (right doped region 7, Para [ 0015, 0021]), wherein the local interconnect (Fig. [1], diffusion layer/ lower electrode [19, 21], Para [ 0021-0027], construed as local interconnect) is connected (electrically connected) to a first side of the first layer (left contact 9, Para [ 0021-0022]) and connected (electrically connected) to a second side of the second layer ( right contact 9, Para [ 0021-0022]).
But Song and Tseng does not disclose explicitly contact layer material made with platinum silicide.
In a similar field of endeavor, HAYASHI discloses contact layer material made with platinum silicide (Fig. [5], platinum silicide layer 18, Para [ 0054]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Song and Tseng in light of HAYASHI teaching “silicide layer is platinum silicide (Fig. [5], platinum silicide layer 18, Para [ 0054])” for further advantage such as high stability, and low resistance.
Regarding claim 18. Son and Tseng disclose the semiconductor device of claim 12, But Son and Tseng do not disclose explicitly wherein: the first doped region is a first conductivity type; and the second doped region is a second conductivity type opposite the first conductivity type.
In a similar field of endeavor, HAYASHI discloses wherein: the first doped region is a first conductivity type (Para [ 0053]); and the second doped region is a second conductivity type opposite the first conductivity type (Para [ 0053]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Son and Tseng in light of HAYASHI teaching “wherein: the first doped region is a first conductivity type (Para [ 0053]); and the second doped region is a second conductivity type opposite the first conductivity type (Para [ 0053])” for further advantage such as enhance carrier mobility and improve device performance.
Regarding claim 19. Son and Tseng disclose the discloses the semiconductor device of claim 12, But Son and Tseng do not disclose explicitly wherein: the first doped region is located in a third doped region of the substrate, the third doped region having a conductivity type opposite the first doped region; and the second doped region is located in a fourth doped region of the substrate, the fourth doped region having a conductivity type opposite the second doped region.
In a similar field of endeavor, HAYASHI discloses wherein: the first doped region (Fig. [5], source/drain diffusion region 16, Para [ 0053]) is located in a third doped region (p-type well 6, Para [ 0049]) of the substrate (Fig. [5], substrate 1, Para [ 0048]), the third doped region (p-type well 6, Para [ 0049]) having a conductivity type opposite the first doped region (Fig. [5], source/drain diffusion region 16, Para [ 0053]); and the second doped region (Fig. [5], source/drain diffusion region 17, Para [ 0053]) is located in a fourth doped region (n-type well 8, Para [ 0049]) of the substrate (Fig. [5], substrate 1, Para [ 0048]), the fourth doped region (n-type well 8, Para [ 0049]) having a conductivity type opposite the second doped region (Fig. [5], source/drain diffusion region 17, Para [ 0053]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Son and Tseng in light of HAYASHI teaching “wherein: the first doped region (Fig. [5], source/drain diffusion region 16, Para [ 0053]) is located in a third doped region (p-type well 6, Para [ 0049]) of the substrate (Fig. [5], substrate 1, Para [ 0048]), the third doped region (p-type well 6, Para [ 0049]) having a conductivity type opposite the first doped region (Fig. [5], source/drain diffusion region 16, Para [ 0053]); and the second doped region (Fig. [5], source/drain diffusion region 17, Para [ 0053]) is located in a fourth doped region (n-type well 8, Para [ 0049]) of the substrate (Fig. [5], substrate 1, Para [ 0048]), the fourth doped region (n-type well 8, Para [ 0049]) having a conductivity type opposite the second doped region (Fig. [5], source/drain diffusion region 17, Para [ 0053])” for further advantage such as enhance carrier mobility and improve device performance.
Allowable Subject Matter
Claims 14-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is the Examiner's Reasons for Allowance:
The prior art fails to disclose and would not have rendered obvious:
Regarding claim 14. wherein the platinum oxide layer extends over a first portion of the first platinum silicide layer and over a second portion of the second platinum silicide layer.
Regarding claim 15. a contact structure contacting the platinum containing layer, wherein the contact structure extends through a platinum oxide layer disposed on the platinum containing layer.
Claim 16 is objected based on the dependency of claim 15.
Regarding claim 17. an isolation structure disposed between the first doped region and the second doped region, wherein the local interconnect is on the isolation structure.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOIN M RAHMAN whose telephone number is (571)272-5002. The examiner can normally be reached 8:30-5:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at 571-272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MOIN M RAHMAN/Primary Examiner, Art Unit 2898