DETAILED ACTION
Election/Restrictions
Applicant’s election without traverse of Group I (Claims 1-13 and 22-23) in the reply filed on 05/15/2026 is acknowledged.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 01/31/2024 and 03/19/2026. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 6-12, 22 and 23 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yang et al. (US 2022/0045183).
As for claim 1, Yang et al. disclose in Figs. 3, 5A-5D and the related text a method, comprising:
forming a substrate trench 301 in a semiconductor substrate 1/2 (Fig. 5A [0083]);
lining the substrate trench with a first insulation layer 3 (Fig. 5B, [0089]);
filling the substrate trench with a first conductive material 4 insulated from the semiconductor substrate by said first insulating layer (Fig. 5B [0094]);
forming a gate trench 304 in the first insulation layer that removes a portion of the first insulation layer adjacent side walls in an upper part of the substrate trench and leaves an integral portion 6 of the first insulation layer in place surrounding the first conductive material at the upper part of the substrate trench (Fig. 5C, [0096]);
lining sidewalls of the upper part of the substrate trench at said gate trench with a second insulating layer 5 (Fig. 5D, [0096]-[0098]); and
depositing a second conductive material 7 in said gate trench 304, said second conductive material 7 insulated from the semiconductor substrate 2 by said second insulating layer 5 and insulated from the first conductive material 4 by said integral portion of the first insulation layer 3 (Fig. 5D, [0098]).
As for claim 6, Yang et al. disclose the method of claim 1, wherein the first and second conductive materials are made of polysilicon ([0094] and [0098]).
As for claim 7, Yang et al. disclose the method of claim 1, wherein the first insulating layer 3 is an oxide and the second insulating layer is a thermal oxide [0093].
As for claim 8, Yang et al. disclose the method of claim 1, wherein the semiconductor substrate 1/2 provides a drain region [0024] of a transistor, further comprising: forming a doped buried region 8 in the semiconductor substrate which provides a body region 8 of the transistor (Fig. 3 [0100]); and forming a doped surface region 9 in the semiconductor substrate over the doped buried region which provides a source region 9 of the transistor (Fig. 3 [0101]).
As for claim 9, Yang et al. disclose the method of claim 8, wherein the first conductive material 4 provides a field plate electrode of the transistor and the second conductive material 7 provides a gate electrode of the transistor [0106].
As for claim 10, Yang et al. disclose the method of claim 8, further comprising: forming an opening extending through the doped surface region 9 and into the doped buried region 8; and filling said opening with a third conductive material 11 (Fig. 3 [0111]).
As for claim 11, Yang et al. disclose the method of claim 10, wherein the third conductive material 11 provides a source contact for the transistor (Fig. 3).
As for claim 12, Yang et al. disclose the method of claim 1, wherein forming the gate trench comprises: forming a mask 303 covering the first conductive material and extending to cover the integral portion 6 of the first insulation layer 3 surrounding the first conductive material (Fig. 5C, [0096]); and performing an oxide selective etch to remove said portion of the first insulation layer 3 not covered by the mask [0096].
As for claim 22, Yang et al. disclose the method of claim 12, further comprising defining dimensions of said mask 303 to provide the covered integral portion 6 of the first insulation layer surrounding the first conductive material 4 with a first lateral thickness, and wherein said second insulating layer 5 has a second lateral thickness greater than the first lateral thickness (fig. 5C).
As for claim 23, Yang et al. disclose the method of claim 1, wherein the integral portion 6 of the first insulation layer 3 surrounding the first conductive material 4 at the upper part of the substrate trench has a first lateral thickness, and wherein said second insulating layer 5 at the upper part of the substrate trench has a second lateral thickness greater than the first lateral thickness (fig. 5D).
Claim Rejections - 35 USC § 103
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Yang et al.
As for claim 13, Yang et al. disclosed substantially the entire claimed invention, as applied to claim 12 above, except defining dimensions of said mask to provide the covered integral portion of the first insulation layer surrounding the first conductive material with a lateral thickness in a range of 1000-1250k, and wherein said second insulating layer has a lateral thickness in a range of 400-800k.
It would have been obvious to one having ordinary skill in the art at the time of the invention was made to include the claimed dimension, in order to optimize the performance of the device. Furthermore, it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980).
Furthermore, it has been held in that the applicant must show that a particular range is critical, generally by showing that the claimed range achieves unexpected results relative to the prior art range. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990). Note that the law is replete with cases in which when the mere difference between the claimed invention and the prior art is some dimensional limitation or other variable within the claims, patentability cannot be found. The instant disclosure does not set forth evidence ascribing unexpected results due to the claimed dimensions. See Gardner v. TEC Systems, Inc., 725 F.2d 1338 (Fed. Cir. 1984), which held that the dimensional limitations failed to point out a feature which performed and operated any differently from the prior art.
Allowable Subject Matter
Claim 2 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of objected subject matter:
“after forming the gate trench and before lining the sidewalls: forming a sacrificial insulating layer on sidewalls of the upper part of the substrate trench and on an upper surface of the first conductive material; and removing a first portion of the sacrificial insulating layer on sidewalls of the upper part of the substrate trench while leaving in place a second portion of the sacrificial insulating layer on the upper surface of the first conductive material”, as recited in claim 2; and
“after depositing the second conductive material in said gate trench: polishing to thin the second conductive material and provide an upper conductive material surface; selectively recessing an upper part of the integral portion of the first insulation layer below said upper conductive material surface; selectively recessing an upper part of the second conductive material in said gate trench below the recessed integral portion of the first insulation layer; selectively recessing an upper part of the first conductive material below the recessed integral portion of the first insulation layer; and forming a third insulating layer on upper surfaces of the recessed upper part of the second conductive material and upper part of the first conductive material”, as recited in claim 3. Claims 4-5 depend among allowable claim 3.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TRANG Q TRAN whose telephone number is (571)270-3259. The examiner can normally be reached on Monday-Thursday (9am-4pm).
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/TRANG Q TRAN/Primary Examiner, Art Unit 2811
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