DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
Acknowledgment is made of applicant's Information Disclosure Statement (IDS) Form PTO-1449. The information disclosed therein was considered.
Election/Restrictions
Applicant's election with traverse of group I (claims 1-12) in the reply filed on 1/9/26 is acknowledged. The traversal is on the ground(s) that the inventions are not independent and distinct. This is not found persuasive. The Examiner apologizes for a typographical mistake in the grouping descriptions of group I and group II. Clearly, group II is the method and group III is the word line device.
Applicant argues with respect to groups I and III that they are not independent and distinct. The inventions are related as noted in the requirement. However, one is drawn to a word line control configuration and the other to a bit line control circuit which are materially different and therefore distinct. Similarly, groups I(III) and II are related. However, group II is a method of operating a device and is distinct from the respective device claims in its requirement of the grounding operations and lack of bit line/word line connections. Furthermore, the searches are not coextensive as outlined in the requirement.
The requirement is still deemed proper and is therefore made FINAL.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, 10 and 11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Gong (US 2015/0206576).
Regarding claim 1, Gong discloses a memory comprising: a bit line (see Figure 4, BL); a negative bit line hybrid boost circuit including: a boost transistor (430); and a metal line capacitor (405) including a first metal line (negative plate) and an at least one second metal line (positive plate) extending adjacent to the first metal line, wherein the first metal line is coupled to the bit line (via decoding transistors) and to a gate of the boost transistor (see Figure 4), and wherein the at least one second metal line is coupled to a drain and source of the boost transistor (see Figure 4).
Regarding claim 2, Gong discloses the memory of claim 1, wherein a length of the metal line capacitor is proportional to a length of the bit line (see paragraph 0042).
Regarding claim 10, Gong discloses the memory of claim 1, wherein the memory is a static random-access memory (see Figure 1).
Regarding claim 11, Gong discloses the memory of claim 1, further comprising: an array of bitcells arranged into columns and rows, wherein the bit line is configured to extend across one of the columns (see Figure 1).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 3, 6, 9 and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gong.
Regarding claim 3, Gong discloses the memory of claim 2, and also teaches that the capacitance tracks the bit line length due to its formation at scale with the memory (see paragraph 0042 for example) and Figure 3 shows the metal lines of the capacitor having what appears to be the same length, but Gong fails to specifically teach the length of the metal line capacitor is substantially equal to the length of the bit line. However, given the suggestion of the capacitor to track the bit line capacitance and the depiction of them with a similar length coupled with the fact that the length of a capacitive “plate” is a result effective variable it would have been obvious to one having ordinary skill at the time of filing to form them of substantially equal length.
Regarding claim 6, Gong discloses the memory of claim 1, wherein the negative bit line hybrid boost circuit further includes: a first transistor (420) having a drain coupled to the first metal line and having a source coupled to ground; but fails to teach a first inverter configured to invert a boost signal and having an output terminal coupled to a gate of the first transistor. However, the Examiner takes official notice that the use of an inverter to drive the gate of pull down transistors as 420 in response to an active low signal is well known in the art and it would have been obvious to one having ordinary skill at the time of filing to provide such an inverter in order to drive the transistor 420.
Regarding claim 9, Gong discloses the memory of claim 1, further comprising: a write driver (see Fgiure 1, 130; Figure 4 440/435); wherein the bit line is configured to couple through the write driver to the negative bit line hybrid boost circuit (see Figure 4). Gong fails to show a column multiplexer. However, the Examiner takes official notice that the use of such column multiplexers for selectively connecting bit lines to drive circuitry. It would have been obvious to one having ordinary skill at the time of filing to provide such a multiplexer in order to provide drive signal to the bit line while reducing the need for multiple drive circuits.
Regarding claim 12, Gong discloses the memory of claim 1, but fails to the memory is incorporated into a cellular telephone. However, it would have been obvious to one having ordinary skill at the time of filing to provide the SRAM of Gong in a cellular telephone in order to realize the benefits of Gong in the memory of the telephone.
Allowable Subject Matter
Claims 4, 5, 7 and 8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 4, the prior art fails to teach or reasonably disclose in combination all the features of the claim in combination with preceding claim limitations including, wherein the bit line is within a first metal layer neighboring a semiconductor substrate, and wherein the first metal line and the at least one second metal line is within a second metal layer neighboring the first metal layer.
Regarding claim 7, the prior art fails to teach or reasonably disclose in combination all the features of the claim in combination with preceding claim limitations including, a second inverter in series with the first inverter; and a third inverter in series with the second inverter and having an output terminal coupled to the at least one second metal line and to the source and the drain of the boost transistor.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
The remaining cited and attached references teach various embodiments of write assist capacitance in SRAM.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DOUGLAS KING whose telephone number is (571)272-2311. The examiner can normally be reached M-F: 9:00AM-5:30PM.
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/DOUGLAS KING/Primary Examiner, Art Unit 2824