CTNF 18/428,984 CTNF 90835 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Information Disclosure Statement The information disclosure statement(s) submitted on June 26, 2025 is/are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement(s) is/are being considered by the examiner. Claim Objections 07-29-01 AIA Claim s 1, 7-13 and 15-18 are objected to because of the following informalities: “and the second S/D EPI structure” should read “to the second S/D EPI structure” (claim 1, line 16); “to the second S/D EPI structure” should read “and the second S/D EPI structure” (claim 7, line 16); in line 1 of each of claims 8-13 and 15-18, “The FET structure” should read “The semiconductor structure” . Appropriate correction is required. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15-aia AIA Claim(s) 1, 2, 6-11, 13-16, 18, 19 and 21 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by US 2022/0052206 A1 (hereinafter “Cheng”) . Regarding claim 1 , Cheng discloses a method of fabricating a semiconductor structure, the method comprising: providing a field effect transistor (FET) structure (the middle gate-all-around (GAA) transistor located in region 202B; Fig. 16A; [0022]) disposed above a substrate (202; Fig. 16D; [0022]), the FET structure comprising a vertical metal gate structure (360B (310, 350); Fig. 16D; [0044]) extending in a first horizontal direction (X direction; Fig. 16A) and being disposed between a first source/drain (S/D) epitaxial (EPI) structure (260B (the one on the left); Fig. 16D; [0037]) and a second S/D EPI structure (260B (the one on the right); Fig. 16D; [0037]) set apart in a second horizontal direction (Y direction; Fig. 16D), the vertical metal gate structure comprising a channel structure ([0043]), the channel structure comprising a plurality of vertically-stacked, horizontal nanosheets (215’; Fig. 16D; [0043]), each nanosheet providing an electrical conducting path from the first S/D EPI structure to the second S/D EPI structure ([0043]), and a gate dielectric material (280, 282; Fig. 16D; [0045]) disposed between the vertical metal gate structure and each of the plurality of vertically-stacked, horizontal nanosheets; removing the substrate below a bottom surface of the FET structure (Fig. 17D; [0057]); removing a portion of vertical metal gate structure and gate dielectric material below a bottom-most nanosheet of the vertically-stacked, horizontal nanosheets (Fig. 19D; [0059]); and removing at least a portion of the bottom-most nanosheet of the vertically-stacked, horizontal nanosheets sufficient to sever its electrical conducting path from the first S/D EPI structure to the second S/D EPI structure (Fig. 19D; [0059]). Regarding claim 2 , Cheng discloses depositing dielectric material (376) onto the bottom surface of the FET structure (Fig. 20D; [0060]). Regarding claim 6 , Cheng discloses the vertical metal gate structure comprises a gate-all-around (GAA) structure ([0015] and [0044]). Regarding claim 7 , Cheng discloses a semiconductor structure, comprising: a substrate (376; Fig. 24D; [0068]); and at least one field effect transistor (FET) structure (the middle gate-all-around (GAA) transistor located in region 202B; Fig. 24A; [0022]) disposed above the substrate, each FET structure comprising: a vertical metal gate structure (360B (310, 350); Fig. 24D; [0044]) extending in a first horizontal direction (X direction; Fig. 24A) and being disposed between a first source/drain (S/D) epitaxial (EPI) structure (260B (the one on the left); Fig. 24D; [0037]) and a second S/D EPI structure (260B (the one on the right); Fig. 24D; [0037]) set apart in a second horizontal direction (Y direction; Fig. 24D), the vertical metal gate structure comprising a channel structure ([0043]), the channel structure comprising a plurality of vertically-stacked, horizontal nanosheets (215’; Fig. 24D; [0043]); a gate dielectric material (280, 282; Fig. 24D; [0045]) disposed between the vertical metal gate structure and each of the plurality of vertically-stacked, horizontal nanosheets; and a backside insulating layer (382; Fig. 24D; [0064]) disposed below (i.e., in a lower place than) the vertical metal gate structure, the first S/D EPI structure and the second S/D EPI structure, wherein at least some (three) of the vertically-stacked, horizontal nanosheets farthest from the backside insulating layer provide an electrical conducting path between the first S/D EPI structure and the second S/D EPI structure in the second horizontal direction through the vertical metal gate structure (Fig. 24D; [0043]), and wherein at least one (the bottommost one) of the vertically-stacked, horizontal nanosheets closest to the backside insulating layer does not provide an electrical conducting path between the first S/D EPI structure and the second S/D EPI structure (Fig. 24D; [0067]). Regarding claim 8 , Cheng discloses each of the vertically-stacked, horizontal nanosheets that does not provide an electrical conducting path between the first S/D EPI structure and the second S/D EPI structure comprises a conducting portion (215’; Fig. 24D; [0067]) and a non-conducting portion (376; Fig. 24D; [0068]). Regarding claim 9 , Cheng discloses the non-conducting portion comprises the substrate (Fig. 24D; [0068]). Regarding claim 10 , Cheng discloses the substrate comprises a dielectric material ([0068]). Regarding claim 11 , Cheng discloses a backside contact (378; Fig. 24D; [0061]) through the substrate to at least one of the first S/D EPI structure or the second S/D EPI structure. Regarding claim 13 , Cheng discloses the vertical metal gate structure comprises a gate-all-around (GAA) structure ([0015] and [0044]). Regarding claim 14 , Cheng discloses a semiconductor structure, comprising: a plurality of field effect transistor (FET) structures (gate all around (GAA) transistors; Fig. 21A; [0022]) extending in a first horizontal direction (X direction; Fig. 21A) and set apart in a second horizontal direction (Y direction; Fig. 21A), wherein each FET structure comprises: a vertical metal gate structure (360A/360B (300/310, 350); Figs. 21C-21D; [0044]) extending in the first horizontal direction and being disposed between a first source/drain (S/D) epitaxial (EPI) structure (260A/260B (the one on the left); Figs. 21C-21D; [0037]) and a second S/D EPI structure (260A/260B (the one on the right); Figs. 21C-21D; [0037]) set apart in the second horizontal direction, the vertical metal gate structure comprising a channel structure ([0043]), the channel structure comprising a plurality of vertically-stacked, horizontal nanosheets (215’; Figs. 21C-21D; [0043]); a gate dielectric material (280, 282; Figs. 21C-21D; [0045]) disposed between the vertical metal gate structure and each of the plurality of vertically-stacked, horizontal nanosheets, at least one frontside dielectric layer (270; Figs. 21C-21D; [0039] and [0062]) disposed above the plurality of FET structures; and a backside insulating structure (376; Figs. 21C-21D; [0060]) disposed below the plurality of FET structures, wherein for a first FET structure (the middle one of the three shown in Fig. 21C) of the plurality of FET structures, the plurality of vertically-stacked, horizontal nanosheets comprises N nanosheets (N= 4 ) and for a second FET structure (the middle one of the three shown in Fig. 21D) of the plurality of FET structures, the plurality of vertically-stacked, horizontal nanosheets comprises N-1 nanosheets (N-1= 3 ) having vertical positions that correspond with the N-1 nanosheets of the first FET structure that are closest to the at least one frontside dielectric layer ([0059] and [0075]). Regarding claim 15 , Cheng discloses the backside insulating structure comprises at least one dielectric layer (376; Figs. 21C-21D; [0060]). Regarding claim 16 , Cheng discloses a backside contact (378; Figs. 21C-21D; [0061]) through the backside insulating structure to at least one of the first S/D EPI structure or the second S/D EPI structure of the first FET structure or the second FET structure. Regarding claim 18 , Cheng discloses each FET structure of the plurality of FET structures comprises a gate-all-around (GAA) structure ([0015] and [0044]). Regarding claim 19 , Cheng discloses a semiconductor structure, comprising: a plurality of field effect transistor (FET) structures (gate all around (GAA) transistors; Fig. 21A; [0022]), each FET structure comprising a vertical metal gate structure (360A/360B (300/310, 350); Figs. 21C-21D; [0044]) extending in a first horizontal direction (X direction; Fig. 21A) and having a first portion disposed between a first source/drain (S/D) epitaxial (EPI) structure (260A/260B (the one on the left); Figs. 21C-21D; [0037]) and a second S/D EPI structure (260A/260B (the one on the right); Figs. 21C-21D; [0037]) set apart in a second horizontal direction (Y direction; Figs. 21C-21D), the vertical metal gate structure comprising a channel structure ([0043]), the channel structure comprising a plurality of vertically-stacked, horizontal nanosheets (215’; Figs. 21C-21D; [0043]), wherein for a first subset of the plurality of FET structures (the three shown in Fig. 21C), the plurality of vertically-stacked, horizontal nanosheets comprises N nanosheets (N= 4 ), and for a second subset of the plurality of FET structures (the three shown in Fig. 21D), the plurality of vertically-stacked, horizontal nanosheets comprises N-1 nanosheets (N-1= 3 ), wherein the bottom-most nanosheet of FET structures in the first subset of the plurality of FET structures is below the bottom-most nanosheet of FET structures in the second subset of the plurality of FET structures ([0059] and [0075]). Regarding claim 21 , Cheng discloses the first subset of the plurality of FET structures comprise a first portion (202A; Fig. 21A; [0022]) of a standard cell (200; Fig. 21A; [0021]) and the second subset of the plurality of FET structures comprise a second portion (202B; Fig. 21A; [0022]) of the standard cell . Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim (s) 3 and 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cheng in view of US 2025/0098245 A1 (hereinafter “Mukesh”) . Regarding claim 3 , Cheng discloses the method of claim 2. Cheng does not explicitly disclose depositing dielectric material onto a bottom surface of the first S/D EPI structure and the second S/D EPI structure. Mukesh teaches in Fig. 17A and related text depositing dielectric material (160; [0106]) onto a bottom surface of the first S/D EPI structure (125-1; [0092]) and the second S/D EPI structure (125-2; [0092]). Cheng and Mukesh are analogous art because they both are directed to semiconductor devices comprising gate-all-around (GAA) field-effect transistors and one of ordinary skill in the art would have had a reasonable expectation of success to modify Cheng with the specified features of Mukesh because they are from the same field of endeavor. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to deposit dielectric material onto a bottom surface of the first S/D EPI structure and the second S/D EPI structure, as taught by Mukesh, in order to use the dielectric material as a replacement substrate after the removal of the original (semiconductor) substrate. Regarding claim 4 , Cheng in view of Mukesh disclose the method of claim 3. Cheng does not disclose creating a backside contact that extends vertically through the dielectric material to electrically couple to the first S/D EPI structure or the second S/D EPI structure. Mukesh teaches in Figs. 18A, 19A and related text creating a backside contact (163-1; [0107]-[0109]) that extends vertically through the dielectric material to electrically couple to the first S/D EPI structure (125-1; [0092]) or the second S/D EPI structure. Cheng and Mukesh are analogous art because they both are directed to semiconductor devices comprising gate-all-around (GAA) field-effect transistors and one of ordinary skill in the art would have had a reasonable expectation of success to modify Cheng in view of Mukesh with the specified features of Mukesh because they are from the same field of endeavor. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to create a backside contact that extends vertically through the dielectric material to electrically couple to the first S/D EPI structure or the second S/D EPI structure, as taught by Mukesh, in order to electrically connect the first S/D EPI structure or the second S/D EPI structure to a subsequently formed backside power delivery network, thereby preventing back-end-of-line (BEOL) routing congestion, resulting in power performance benefits (Mukesh: Fig. 20A; [0112]) . 07-22-aia AIA Claim (s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cheng in view of Mukesh as applied to claim 4 above, and further in view of US 2024/0363491 A1 (hereinafter “Yun”) . Regarding claim 5 , Cheng in view of Mukesh disclose the method of claim 4. Cheng in view of Mukesh do not explicitly disclose forming, on a bottom surface of the substrate, a backside metal structure that is electrically coupled to the backside contact. Yun teaches in Fig. 1 and related text forming, on a bottom surface (102L; [0017]) of the substrate (102; [0017]-[0018]), a backside metal structure (120; [0043]) that is electrically coupled to the backside contact (122, 124; [0043]). Cheng, Mukesh and Yun are analogous art because they each are directed to semiconductor devices comprising gate-all-around (GAA) field-effect transistors and one of ordinary skill in the art would have had a reasonable expectation of success to modify Cheng in view of Mukesh with the specified features of Yun because they are from the same field of endeavor. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to form, on a bottom surface of the substrate, a backside metal structure that is electrically coupled to the backside contact, as taught by Yun, in order to provide a backside power distribution network, thereby simplifying the middle-of-line (MOL) portion and/or the back-end-of-line (BEOL) portion of device fabrication (Yun: [0002]-[0003]) . 07-21-aia AIA Claim (s) 12 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cheng in view of Yun . Regarding claim 12 , Cheng discloses the semiconductor structure of claim 11. Cheng does not disclose the backside contact is coupled to a backside metal structure disposed on a bottom surface of the substrate. Yun teaches in Fig. 1 and related text the backside contact (122, 124; [0043]) is coupled to a backside metal structure (120; [0043]) disposed on a bottom surface (102L; [0017]) of the substrate (102; [0017]-[0018]). Cheng and Yun are analogous art because they both are directed to semiconductor devices comprising gate-all-around (GAA) field-effect transistors and one of ordinary skill in the art would have had a reasonable expectation of success to modify Cheng with the specified features of Yun because they are from the same field of endeavor. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to couple the backside contact to a backside metal structure disposed on a bottom surface of the substrate, as taught by Yun, in order to provide a backside power distribution network, thereby simplifying the middle-of-line (MOL) portion and/or the back-end-of-line (BEOL) portion of device fabrication (Yun: [0002]-[0003]). Regarding claim 17 , Cheng discloses the semiconductor structure of claim 16. Cheng does not disclose the backside contact is coupled to a backside metal structure disposed on a bottom surface of the backside insulating structure. Yun teaches in Fig. 1 and related text the backside contact (122, 124; [0043]) is coupled to a backside metal structure (120; [0043]) disposed on a bottom surface (102L; [0017]) of the backside insulating structure (102; [0017]-[0018]). Cheng and Yun are analogous art because they both are directed to semiconductor devices comprising gate-all-around (GAA) field-effect transistors and one of ordinary skill in the art would have had a reasonable expectation of success to modify Cheng with the specified features of Yun because they are from the same field of endeavor. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to couple the backside contact to a backside metal structure disposed on a bottom surface of the backside insulating structure, as taught by Yun, in order to provide a backside power distribution network, thereby simplifying the middle-of-line (MOL) portion and/or the back-end-of-line (BEOL) portion of device fabrication (Yun: [0002]-[0003]) . 07-21-aia AIA Claim (s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cheng in view of US 2019/0074297 A1 (hereinafter “Kishishita”) . Regarding claim 20 , Cheng discloses the semiconductor structure of claim 19. Cheng does not explicitly disclose the first subset of the plurality of FET structures comprise a first standard cell and the second subset of the plurality of FET structures comprise a second standard cell. Kishishita teaches in Fig. 1 and related text the first subset of the plurality of FET structures (P1, N1; [0040]-[0041]) comprise a first standard cell (1; [0039]) and the second subset of the plurality of FET structures (P2, N2; [0040]-[0041]) comprise a second standard cell (2; [0039]). Cheng and Kishishita are analogous art because they both are directed to semiconductor devices comprising gate-all-around (GAA) field-effect transistors and one of ordinary skill in the art would have had a reasonable expectation of success to modify Cheng with the specified features of Kishishita because they are from the same field of endeavor. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to form the first subset of the plurality of FET structures to comprise a first standard cell and the second subset of the plurality of FET structures to comprise a second standard cell, as taught by Kishishita, in order to facilitate manufacturing of a semiconductor integrated circuit device including a nanowire FET, and reduce process-induced variations, thus improving the yield (Kishishita: [0016]) . 07-21-aia AIA Claim (s) 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cheng in view of US 2023/0138711 A1 (hereinafter “Huang”) . Regarding claim 22 , Cheng discloses the semiconductor structure of claim 21. Cheng does not disclose the standard cell comprises a static random access memory (SRAM) standard cell, a digital logic standard cell, or an analog standard cell. Huang teaches in Fig. 1 and related text the standard cell (120, 122; [0014]) comprises a static random access memory (SRAM) standard cell, a digital logic standard cell ([0014]), or an analog standard cell. Cheng and Huang are analogous art because they both are directed to semiconductor devices comprising gate-all-around (GAA) field-effect transistors and one of ordinary skill in the art would have had a reasonable expectation of success to modify Cheng with the specified features of Huang because they are from the same field of endeavor. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to form the standard cell to comprise a digital logic standard cell, as taught by Huang, in order to reduce design effort, enhance circuit performance, and reduce circuit areas (Huang: [0002] and [0012]). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to PETER M ALBRECHT whose telephone number is (571)272-7813. The examiner can normally be reached M-F 9:30 AM - 6:30 PM (CT). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached at (571) 272-1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /PETER M ALBRECHT/Primary Examiner, Art Unit 2811 Application/Control Number: 18/428,984 Page 2 Art Unit: 2811 Application/Control Number: 18/428,984 Page 3 Art Unit: 2811 Application/Control Number: 18/428,984 Page 4 Art Unit: 2811 Application/Control Number: 18/428,984 Page 5 Art Unit: 2811 Application/Control Number: 18/428,984 Page 6 Art Unit: 2811 Application/Control Number: 18/428,984 Page 7 Art Unit: 2811 Application/Control Number: 18/428,984 Page 8 Art Unit: 2811 Application/Control Number: 18/428,984 Page 9 Art Unit: 2811 Application/Control Number: 18/428,984 Page 10 Art Unit: 2811 Application/Control Number: 18/428,984 Page 11 Art Unit: 2811 Application/Control Number: 18/428,984 Page 12 Art Unit: 2811 Application/Control Number: 18/428,984 Page 13 Art Unit: 2811 Application/Control Number: 18/428,984 Page 14 Art Unit: 2811 Application/Control Number: 18/428,984 Page 15 Art Unit: 2811
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