DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
1. This Office Action is in response to Amendment filed on date: 2/17/2026.
Claims 1-25 are currently pending.
Claims 21-25 are newly added.
Claims 1, 9, 15 and 22 are independent claims.
Response to Arguments
2. Applicant's arguments, see in pages 9-19 in the submitted Remarks, filed on 2/17/2026, have been fully considered but are moot in view of the new ground(s) of rejection.
Claim Objection
3. Claims 22 and 25 are objected to because of the following informalities: Regarding claim 22, the limitation “a second transistor having a first and second transistor terminals and a control terminal” in line 3 should be deleted because it is duplicated with the limitation “a second transistor having first and second transistor terminals and a control terminal” in line 5. It notes that the terms “a first and second transistor terminals” in line 3 should be changed to --- first and second transistor terminals ---. Regarding claim 24, in line 1, “Electronic device of Claim 22” should be changed to --- The electronic device of Claim 22 ---.
Regarding claim 25, the claim is identical with claim 21. Both claims 21 and 25 are depended from claim 1. Therefore, claim 25 should be cancelled.
Examiner Notes
4. Examiner cites particular paragraphs, columns and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
Claim Rejections - 35 USC § 102
5. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
6. Claims 1-3, 6, 8, 21, 25 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Iwamizu et al. (US. Pub. 2019/0286181; hereinafter “Iwamizu”).
Regarding claim 1, Iwamizu discloses, in Fig. 1, an electronic device (a semiconductor device 1 in Fig. 1), comprising: a transistor (a transistor 14) having first and second transistor terminals (a first transistor terminal is a drain terminal of the transistor 14 and a second transistor terminal is a source terminal of the transistor 14) and a control terminal (a control terminal is a gate terminal of the transistor 14); a control circuit (a control circuit 16) connected to the control terminal (the gate terminal); a first device terminal (a device terminal 12) connected to the first transistor terminal (the drain terminal); a second device terminal (a device terminal 13) directly connected to the second transistor terminal (the source terminal) and to a terminal of a second transistor (a source terminal of a transistor 19); and a clamp circuit (an active clamping circuit 22) connected between the first transistor terminal (the drain terminal) and the control terminal (the gate terminal)(see Fig. 1).
Regarding claim 2, Iwamizu discloses the electronic device of claim 1, wherein the control terminal is not directly connected to any device terminal (Fig. 1 shows the control terminal or gate terminal of the transistor 14 is not directly connected to any device terminal).
Regarding claim 3, Iwamizu discloses the electronic device of claim 1, wherein the clamp circuit (22 in Fig. 1) includes a p-n junction diode (a p-n junction diode 24) and a Zener diode (a Zener diode 23) connected in series with one another (see Fig. 1) between the first transistor terminal (a drain terminal of the transistor 14) and the control terminal (a control gate terminal of the transistor 14).
Regarding claim 6, Iwamizu discloses the electronic device of claim 3, wherein: the p-n junction diode (the p-n junction diode 24 in Fig. 1) includes a first anode and a first cathode, the first cathode directly connected to the control terminal (Fig. 1 shows that a cathode of the diode 24 directly connected to the control gate terminal of the transistor 14) includes a second anode and a second cathode, the second anode directly connected to the first anode, and the second cathode directly connected to the first transistor terminal (Fig. 1 shows that an anode of the Zener diode 23 directly connected to the anode of the p-n junction diode 24 and a cathode of the Zener diode 23 directly connected to the drain terminal of the transistor 14).
Regarding claim 8, Iwamizu discloses the electronic device of claim 1, wherein: the first transistor terminal is a drain (a drain terminal of the transistor 14 in Fig. 1); the second transistor terminal is a source (a source terminal of the transistor 14); and the control terminal is a gate (a gate terminal of the transistor 14).
Regarding claim 21, Iwamizu discloses the electronic device of claim 1, wherein the clamp circuit (22 in Fig. 1) includes only a p-n junction diode (24) and a Zener diode (23) connected in series with one another between the first transistor terminal (the drain terminal of the transistor 14) and the control terminal (the gate terminal of the transistor 14)(see Fig. 1).
Regarding claim 25, Iwamizu discloses the electronic device of claim 1, wherein the clamp circuit (22 in Fig. 1) includes only a p-n junction diode (24) and a Zener diode (23) connected in series with one another between the first transistor terminal (the drain terminal of the transistor 14) and the control terminal (the gate terminal of the transistor 14)(see Fig. 1).
7. Claims 1-4, 7-8, 21-25 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kitagawa et al. (US. Pub. 2024/0259018 ; hereinafter “Kitagawa”).
Regarding claim 1, Kitagawa discloses, in Fig. 5, an electronic device (a drive circuit 34 in Fig. 5), comprising: a transistor (a transistor 3) having first and second transistor terminals (a first transistor terminal is a drain terminal of the transistor 3 and a second transistor terminal is a source terminal of the transistor 3) and a control terminal (a control terminal is a gate terminal of the transistor 3); a control circuit (a driver 7) connected to the control terminal (the gate terminal); a first device terminal (an output terminal OUT, see annotated Fig. 5 below) connected to the first transistor terminal (the drain terminal of the transistor 3); a second device terminal (a terminal M2) directly connected to the second transistor terminal (the source terminal of the transistor 3) and to a terminal of a second transistor (a drain terminal of a transistor 4); and a clamp circuit (a first clamp circuit 9) connected between the first transistor terminal (the drain terminal) and the control terminal (the gate terminal)(see Fig. 5).
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Regarding claim 2, Kitagawa discloses the electronic device of claim 1, wherein the control terminal is not directly connected to any device terminal (Fig. 5 shows the gate terminal of the transistor 3 is not directly connected to any device terminal).
Regarding claim 3, Kitagawa discloses the electronic device of claim 1, wherein the clamp circuit (9 in Fig. 5) includes a p-n junction diode (a p-n junction diode 30) and a Zener diode (a Zener diode 31) connected in series with one another (see Fig. 5) between the first transistor terminal (the drain terminal of the transistor 3) and the control terminal (the gate terminal of the transistor 3).
Regarding claim 4, Kitagawa discloses the electronic device of claim 3, further comprising a resistor (a resistor 11) connected between the control terminal (the gate terminal of transistor 3) and the second transistor terminal (the source of transistor 3).
Regarding claim 7, Kitagawa discloses the electronic device of claim 1, further comprising a resistor (a resistor 11) connected between the control terminal (the gate terminal of transistor 3) and the second transistor terminal (the source of transistor 3).
Regarding claim 8, Kitagawa discloses the electronic device of claim 1, wherein: the first transistor terminal is a drain (a drain terminal of the transistor 3 in Fig. 5); the second transistor terminal is a source (a source terminal of the transistor 3); and the control terminal is a gate (a gate terminal of the transistor 3).
Regarding claim 21, Kitagawa discloses the electronic device of claim 1, wherein the clamp circuit (9 in Fig. 5) includes only a p-n junction diode (30) and a Zener diode (31) connected in series with one another between the first transistor terminal (the drain terminal of the transistor 3) and the control terminal (the gate terminal of the transistor 3)(see Fig. 5).
Regarding claim 22, Kitagawa discloses, in Fig. 5, an electronic device (a drive circuit 34 in Fig. 5), comprising:
a first transistor (a transistor 3) having first and second transistor terminals (a first transistor terminal is a drain terminal of the transistor 3 and a second transistor terminal is a source terminal of the transistor 3) and a control terminal (a control terminal is a gate terminal of the transistor 3);
a second transistor (a transistor 4) having a first and second transistor terminals (a first transistor terminal is a drain terminal of the transistor 4 and a second transistor terminal is a source terminal of the transistor 4) and a control terminal (a control terminal is a gate terminal of the transistor 4);
a control circuit (a driver 7) connected to the control terminal (the gate terminal) of the first transistor (the transistor 3);
a second transistor (a transistor 4) having first and second transistor terminals (a first transistor terminal is a drain terminal of the transistor 4 and a second transistor terminal is a source terminal of the transistor 4) and a control terminal (a control terminal is a gate terminal of the transistor 4);
a first device terminal (an output terminal OUT, see annotated Fig. 5 below) connected to the first transistor terminal of the first transistor (the drain terminal of the transistor 3);
a second device terminal (a terminal M2) connected to the second transistor terminal of the first transistor (the source terminal of the transistor 3) and to the first transistor terminal of the second transistor (the drain terminal of the transistor 4);
a first clamp circuit (a first clamp circuit 9) connected between the first transistor terminal and the control terminal of the first transistor (see Fig. 5), wherein the first clamp circuit includes a p-n junction diode (a p-n junction diode 30) and a Zener diode (a Zener diode 31) connected in series with one another between the first transistor terminal and the control terminal of the first transistor (see Fig. 5); and
a second clamp circuit (a second clamp circuit 10) connected between the first transistor terminal and the control terminal of the second transistor (see Fig. 5), wherein the second clamp circuit includes a p-n junction diode (a p-n junction diode 32) and a Zener diode (a Zener diode 33) connected in series with one another between the first transistor terminal and the control terminal of the second transistor (see Fig. 5).
Regarding claim 23, Kitagawa discloses the electronic device of Claim 22, wherein the control circuit (the driver 8) is further connected to the control terminal of the second transistor (the gate terminal of the transistor 4).
Regarding claim 24, Kitagawa discloses Electronic device of Claim 22 wherein the source of the first transistor is directly connected to the drain of the second transistor (as shown in Fig. 5, the source terminal of the transistor 3 is directly connected to the drain of the transistor 4) (see Fig. 5).
Regarding claim 25, Kitagawa discloses the electronic device of claim 1, wherein the clamp circuit (9 in Fig. 5) includes only a p-n junction diode (30) and a Zener diode (31) connected in series with one another between the first transistor terminal (the drain terminal of the transistor 3) and the control terminal (the gate terminal of the transistor 3)(see Fig. 5).
Claim Rejections - 35 USC § 103
8. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
9. Claims 4-5 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Iwamizu in view of Wada et al. (US. Pub. 2019/0260371; hereinafter “Wada”).
Regarding claim 4, Iwamizu discloses the electronic device of claim 3, except for explicitly specifying that further comprising a resistor connected between the control terminal and the second transistor terminal.
Wada discloses, in Fig. 1 and 10, an electronic device (a semiconductor device 6 in Fig. 1 or 6p in Fig. 10), comprising: a transistor (13 in Fig. 1 or 29 in Fig. 10) having first and second transistor terminals (drain and source terminals) and a control terminal (a gate terminal); a control circuit (a control circuit coupled to an input terminal 3) connected to the control terminal; a first device terminal (4) connected to the first transistor terminal (the drain terminal); a second device terminal (5) connected to the second transistor terminal (a source terminal); and a clamp circuit (8) connected between the first transistor terminal and the control terminal (see Fig. 1 and 10), wherein a resistor (9) connected between the control terminal (the gate terminal of the transistor 13 or 29) and the second transistor terminal (the source terminal of the transistor 13 in Fig. 1 or 29 in Fig. 10).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to employ the semiconductor device of Iwamizu by having a resistor connected between the control terminal and the second transistor terminal as taught by Wada for purpose of preventing an unstable state of potential operation of the transistor, improving stability in operation.
Regarding claim 5, Iwamizu and Wada disclose the electronic device of claim 4, Iwamizu further teaches wherein: the p-n junction diode (the p-n junction diode 24 in Fig. 1) includes a first anode and a first cathode, the first cathode directly connected to the control terminal (Fig. 1 shows that a cathode of the diode 24 directly connected to the control gate terminal of the transistor 14); and the Zener diode (the Zener diode 23) includes a second anode and a second cathode, the second anode directly connected to the first anode, and the second cathode directly connected to the first transistor terminal (Fig. 1 shows that an anode of the Zener diode 23 directly connected to the anode of the p-n junction diode 24 and a cathode of the Zener diode 23 directly connected to the drain terminal of the transistor 14).
Regarding claim 7, Iwamizu discloses the electronic device of claim 1, except for explicitly specifying that further comprising a resistor connected between the control terminal and the second transistor terminal.
Wada discloses, in Fig. 1 and 10, an electronic device (a semiconductor device 6 in Fig. 1 or 6p in Fig. 10), comprising: a transistor (13 in Fig. 1 or 29 in Fig. 10) having first and second transistor terminals (drain and source terminals) and a control terminal (a gate terminal); a control circuit (a control circuit coupled to an input terminal 3) connected to the control terminal; a first device terminal (4) connected to the first transistor terminal (the drain terminal); a second device terminal (5) connected to the second transistor terminal (a source terminal); and a clamp circuit (8) connected between the first transistor terminal and the control terminal (see Fig. 1 and 10), wherein a resistor (9) connected between the control terminal (the gate terminal of the transistor 13 or 29) and the second transistor terminal (the source terminal of the transistor 13 in Fig. 1 or 29 in Fig. 10).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to employ the semiconductor device of Iwamizu by having a resistor connected between the control terminal and the second transistor terminal as taught by Wada for purpose of preventing an unstable state of potential operation of the transistor, improving stability in operation.
10. Claims 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over Kitagawa in view of Takuma et al. (US. Pub. 2022/0352145; hereinafter “Takuma”).
Regarding claim 5, Kitagawa discloses the electronic device of claim 4, wherein: the p-n junction diode (the p-n junction diode 30 in Fig. 5) includes a first anode and a first cathode; and the Zener diode (the Zener diode 31) includes a second anode and a second cathode.
Kitagawa does not disclose the first cathode directly connected to the control terminal and the second anode directly connected to the first anode, and the second cathode directly connected to the first transistor terminal.
Takuma discloses, in Figs. 2-3, a semiconductor device (1 in Fig. 2) comprising an active clamp circuit (26 in Fig. 3), wherein the active clamp circuit (26) comprising a p-n junction diode (D) includes a first anode and a first cathode, the first cathode directly connected to a control terminal of a transistor (Fig. 3 shows that a cathode of the diode D directly connected to a control gate terminal of a transistor 9); and a Zener diode (DZ) includes a second anode and a second cathode, the second anode directly connected to the first anode, and the second cathode directly connected to the first transistor terminal (Fig. 3 shows that an anode of the Zener diode DZ directly connected to the anode of the p-n junction diode D and a cathode of the Zener diode DZ directly connected to the drain terminal of the transistor 9). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to employ the drive circuit of Kitagawa by having the clamp circuit so that the first cathode of the p-n junction diode directly connected to the control terminal of the transistor and the second anode of the p-n junction diode directly connected to the first anode, and the second cathode of the Zener diode directly connected to the first transistor terminal as taught by Takuma for purpose of enhancing protection the power transistor from a counter electromotive force and improvement of active clamp resistance quantity is aimed by simple circuit structure, so that outstanding ON-resistance and outstanding active clamp resistance quantity are compatible.
Regarding claim 6, Kitagawa discloses the electronic device of claim 3, wherein: the p-n junction diode (the p-n junction diode 30 in Fig. 5) includes a first anode and a first cathode; and the Zener diode (the Zener diode 31) includes a second anode and a second cathode. Kitagawa does not disclose the first cathode directly connected to the control terminal and the second anode directly connected to the first anode, and the second cathode directly connected to the first transistor terminal.
Takuma discloses, in Figs. 2-3, a semiconductor device (1 in Fig. 2) comprising an active clamp circuit (26 in Fig. 3), wherein the active clamp circuit (26) comprising a p-n junction diode (D) includes a first anode and a first cathode, the first cathode directly connected to a control terminal of a transistor (Fig. 3 shows that a cathode of the diode D directly connected to a control gate terminal of a transistor 9); and a Zener diode (DZ) includes a second anode and a second cathode, the second anode directly connected to the first anode, and the second cathode directly connected to the first transistor terminal (Fig. 3 shows that an anode of the Zener diode DZ directly connected to the anode of the p-n junction diode D and a cathode of the Zener diode DZ directly connected to the drain terminal of the transistor 9). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to employ the drive circuit of Kitagawa by having the clamp circuit so that the first cathode of the p-n junction diode directly connected to the control terminal of the transistor and the second anode of the p-n junction diode directly connected to the first anode, and the second cathode of the Zener diode directly connected to the first transistor terminal as taught by Takuma for purpose of enhancing protection the power transistor from a counter electromotive force and improvement of active clamp resistance quantity is aimed by simple circuit structure, so that outstanding ON-resistance and outstanding active clamp resistance quantity are compatible.
Allowable Subject Matter
11. Claims 9-20 are allowed over the prior arts of record.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 9, the cited references, alone or in combination, do not disclose nor fairly suggest:
“ … a test capacitor adapted to be connected to the first device terminal; and a precharge circuit configured to selectively provide a precharge current to the first device terminal; wherein the controller is configured to: operate the precharge circuit in a first precharge mode to provide the precharge current to the first device terminal to precharge the test capacitor when the test capacitor is connected to the first device terminal, and then operate the precharge circuit in a second precharge mode to stop the precharge current to the first device terminal; selectively operate the switching circuit in a first switching circuit mode to connect the first inductor terminal to a precharge load to develop a test current in the test inductor, and in a second switching circuit mode to connect the first inductor terminal to the output of the switching circuit to cause the test current to flow into the first device terminal while the precharge circuit is in the second precharge mode; and operate the measurement circuit to measure the voltage between the first and second device terminals while the switching circuit is in the second switching circuit mode and the precharge circuit is in the second precharge mode” in combination with all other elements as claimed in claim 9.
Regarding claim 15, the cited references, alone or in combination, do not disclose nor fairly suggest:
“ … connecting a second capacitor terminal of the test capacitor to a third device terminal of the DUT; precharging the test capacitor using a precharge circuit; disconnecting the precharge circuit from the test capacitor; precharging a test inductor to develop a test current in the test inductor; connecting the test inductor to cause the test current to flow from the test inductor into the first device terminal while the precharge circuit is disconnected from the test capacitor; and testing the transistor of the DUT while the test current is flowing into the first device terminal” in combination with all other elements as claimed in claim 15.
As to claim(s) 10-14, the claims are allowed as they further limit allowed claim 9.
As to claim(s) 16-20, the claims are allowed as they further limit allowed claim 15.
Conclusion
12. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THANG LE whose telephone number is (571)272-9349. The examiner can normally be reached on Monday thru Friday 7:30AM-5:00PM EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Huy Phan can be reached on (571) 272-7924. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/THANG X LE/Primary Examiner, Art Unit 2858
5/26/2026
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