Prosecution Insights
Last updated: October 01, 2026
Application No. 18/429,228

LASER ANNEAL FORMED NANOSHEET LDMOS TRANSISTOR

Non-Final OA §102§103
Filed
Jan 31, 2024
Priority
Jun 09, 2023 — provisional 63/507,277
Examiner
TRAN, TRANG Q
Art Unit
2811
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Texas Instruments Incorporated
OA Round
1 (Non-Final)
81%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
89%
With Interview

Examiner Intelligence

Grants 81% — above average
81%
Career Allowance Rate
600 granted / 738 resolved
+13.3% vs TC avg
Moderate +7% lift
Without
With
+7.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 8m
Avg Prosecution
47 currently pending
Career history
776
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
47.1%
+7.1% vs TC avg
§102
35.5%
-4.5% vs TC avg
§112
16.0%
-24.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 738 resolved cases

Office Action

§102 §103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . DETAILED ACTION Election/Restrictions Applicant’s election without traverse of Group I (Claims 1-11) in the reply filed on 08/03/2026 is acknowledged. Claims 12-20 have been withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 08/03/2026. Applicant's election with traverse of Species A (Figs. 1AA-1AZ) in the reply filed on 08/03/2026 is acknowledged. Applicant argues that Species A and B (Figs. 1AA-1AZ and 1BA-1BI) should be in a same species. Examiner agreed that Species A and B be joined. The requirement is still deemed proper and is therefore made FINAL. Information Disclosure Statement The information disclosure statement (IDS) submitted on 01/31/2024. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1-3 and 11 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Huang et al. (US 2024/0072156). As for claim 1, Huang et al. disclose in Figs. 1-11 and the related a microelectronic device, comprising: first and second doped semiconductor regions 130 over a semiconductor substrate 100; and a semiconductor nanosheet layer 114 connected between the first and second semiconductor regions and having a bandgap greater than 1.5 eV ([0014] of Huang et al. teach a semiconductor nanosheet layer 114 comprise the same material (silicon carbide) as claimed invention, therefore it’s having a bandgap greater than 1.5 eV. As for claim 2, Huang et al. disclose the microelectronic device as recited in Claim 1, further comprising: a gate electrode 138 spaced apart from the nanosheet layer (Fig. 11); and a gate dielectric layer 136 between the nanosheet layer and the gate electrode (Fig. 11). As for claim 3, Huang et al. disclose the microelectronic device as recited in Claim 2, wherein the semiconductor nanosheet layer 114 is one of first and second semiconductor nanosheet layers connected between the first and second doped semiconductor regions (Fig. 11), and the gate electrode 138 and the gate dielectric layer 136 are between the first and second semiconductor nanosheet layers (Fig. 11). As for claim 8, Huang et al. disclose the microelectronic device as recited in Claim 2, further comprising a gate trench G1/G2 extending through the semiconductor nanosheet layer, the gate electrode 138 extending from the gate trench (Fig. 1-11). As for claim 11, Huang et al. disclose the microelectronic device as recited in Claim 1, wherein the semiconductor nanosheet layer 114 comprises silicon carbide [0014]. Claim Rejections - 35 USC § 103 The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Huang et al.. As for claim 10, Huang et al. disclose the microclectronic device recited in Claim 1, except the semiconductor nanosheet layer has a thickness greater than 10 nanometers. It would have been obvious to one having ordinary skill in the art at the time of the invention was made to include the semiconductor nanosheet layer has a thickness greater than 10 nanometers, in order to optimize the performance of the device. Furthermore, it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980). Furthermore, it has been held in that the applicant must show that a particular range is critical, generally by showing that the claimed range achieves unexpected results relative to the prior art range. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990). Note that the law is replete with cases in which when the mere difference between the claimed invention and the prior art is some dimensional limitation or other variable within the claims, patentability cannot be found. The instant disclosure does not set forth evidence ascribing unexpected results due to the claimed dimensions. See Gardner v. TEC Systems, Inc., 725 F.2d 1338 (Fed. Cir. 1984), which held that the dimensional limitations failed to point out a feature which performed and operated any differently from the prior art. Allowable Subject Matter Claims 4-7 and 9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: the first doped semiconductor region is a source region and the second doped semiconductor region is a drain region, the source and drain regions having a first conductivity type and a first average dopant concentration, and further comprising a drain drift region having the first conductivity type and a lower second dopant concentration in the semiconductor nanosheet layer and extending from the drain region toward the source region, and a channel region between the drain drift region and the source region. Claims 5-7 and 9 depend objected claim 4. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to TRANG Q TRAN whose telephone number is (571)270-3259. The examiner can normally be reached on Monday-Thursday (9am-4pm). If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached on 5712721670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /TRANG Q TRAN/Primary Examiner, Art Unit 2811
Read full office action

Prosecution Timeline

Jan 31, 2024
Application Filed
Sep 09, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
81%
Grant Probability
89%
With Interview (+7.3%)
2y 8m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 738 resolved cases by this examiner. Grant probability derived from career allowance rate.

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