DETAILED ACTION
Table of Contents
I. Notice of Pre-AIA or AIA Status 3
II. Claim Rejections - 35 USC § 103 3
A. Claims 1-7, 11-14, 17, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0157722 (“Bouche”) in view of US 2020/0098681 (“Kim”). 3
B. Claims 8-10, 15, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Bouche in view of Kim, as applied to claims 4 and 11 above, and further in view of US 2022/0367454 (“Chung”). 12
C. Claims 18 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Bouche in view of Kim and US 2019/0214502 (“Xu”). 20
III. Response to Arguments 23
Conclusion 24
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I. Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
II. Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
A. Claims 1-7, 11-14, 17, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0157722 (“Bouche”) in view of US 2020/0098681 (“Kim”).
Claim 1 reads,
1. (Currently Amended) An integrated circuit device, comprising:
[1] a substrate having a plurality of device regions extending in a first horizontal direction;
[2] a plurality of gate electrodes on the plurality of device regions extending in a second horizontal direction that is orthogonal to the first horizontal direction;
[3a] a plurality of source/drain regions between a pair of gate electrodes adjacent to each other in the first horizontal direction among the plurality of gate electrodes,
[3b] each of the plurality of source/drain regions being on a portion of the plurality of a respective one of device regions;
[4] a plurality of gate cut regions, each of the plurality of gate cut regions cutting the plurality of gate electrodes and extending in the first horizontal direction; and
[5a] a plurality of contact structures each including a contact body portion integrally formed with a plurality of contact finger portions,
[5b] the contact body portion filling a respective one of the plurality of gate cut regions and extending in the first horizontal direction, and
[5c] each of the plurality of contact finger portions extending in the second horizontal direction from the contact body portion and being connected to a respective one of the plurality of source/drain regions.
With regard to claim 1, Bouche discloses,
1. (Currently Amended) An integrated circuit device, comprising:
[1] a substrate 102 [¶ 48] having a plurality of device regions [e.g. fins 104 (¶ 48)] extending in a first horizontal direction X [Figs. 1, 2, 3A];
[2] a plurality of gate electrodes 212 [¶¶ 66, 69] on the plurality of device regions extending in a second horizontal direction Y that is orthogonal to the first horizontal direction X [as shown in Figs. 2 and 3A];
[3a] a plurality of source/drain regions 114-1, 114-2 [¶¶ 48, 59; Figs. 5A, 7I, 7L] between a pair of gate electrodes 212 adjacent to each other in the first horizontal direction X among the plurality of gate electrodes [as shown in Figs. 2 and 5A],
[3b] each of the plurality of source/drain regions 114-1, 114-2 [¶¶ 48, 59] being on portions of a respective one of the plurality of device regions 104 [as shown in Figs. 2 and 5A];
[4] a plurality of gate cut regions 312-2 [¶¶ 16-20, 73-76, 83, 96 (infra)], each of the gate cut regions cutting the plurality of gate electrodes 212 and extending in the first horizontal direction X [as shown in Figs. 3A and Fig. 7B]; and
[5a] a plurality of contact structures [322 in Figs. 3A, 7I, 7L (¶¶ 76, 96, 113-115)] each including a contact body portion [i.e. vertical column portion of 322 extending from the bottom of the substrate to the top of the etch stop layer 752 in Fig. 7L] integrally formed with a … contact finger portion… [i.e. portion of 322 extending in Y direction from vertical portion of 322 in Figs. 3A, 7I, 7L],
[5b] the contact body portion [vertical column portion of 322 (Figs. 3A, 7I, 7L)] filling a respective one of the plurality of gate cut regions 312-2 [as shown in Fig. 3A, 7I, 7L] and extending in the first horizontal direction X [as shown in Fig. 3A], and
[5c] each … contact finger portion… [i.e. Y extension of 322 (Figs. 7I, 7L)] extending in the second horizontal direction Y from the plurality of contact body portions [i.e. vertical column portion of 322 (Fig. 7A)] and being connected to a respective one of the plurality of source/drain regions 114 [by means of the S/D contact trench 508 (¶ 104), as shown in Figs. 7I and 7L].
With regard to feature [4] and [5a]-[5c] of claim 1, while Fig. 3A shows only one gate cut region with one backside power rail “BPR”, Bouche explains that there are “one or more BPRs” formed by the process delineated in Fig. 6. In this regard, Bouche states,
[0016] FIGS. 6A-6B provide a flow diagram of an example method of manufacturing an IC structure with one or more BPRs with self-aligned vias to trench contacts, according to one embodiment of the disclosure.
[0017] FIGS. 7A-7L are various views illustrating different example stages in the manufacture of an IC structure with one or more BPRs with self-aligned vias to trench contacts using the method of FIGS. 6A-6B, according to some embodiments of the present disclosure.
[0096] Although the operations of the method 600 are illustrated once each and in a particular order, the operations may be performed in any suitable order and repeated as desired. For example, one or more operations may be performed in parallel to manufacture, substantially simultaneously, multiple IC structures with one or more BPRs with self-aligned vias to trench contacts as described herein. In another example, the operations may be performed in a different order to reflect the structure of a particular device assembly in which one or more BPRs with self-aligned vias to trench contacts as described herein will be included.
(Bouche: ¶¶ 16, 17, 96; emphasis added)
See, also, ¶¶ 18-20.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include a plurality of BPRs “according to the operations of the method 600” (id.), because Bouche explicitly states that more than one can be made (id.).
In order to form more than one, i.e. a plurality of, “BPRs” (id.) “according to the operations of the method 600” (id.), the openings 734, which includes three openings, 734-1, 734-2, and 734-3, as shown in Fig. 7G, forming the gate cuts 312-2 through a plurality of gates 212, must also be formed (¶¶ 105-107) and then filled with the conductive material 322, as shown in Figs. 7H and 7I (¶¶ 113-118). Each of Figs. 7H and 7I shows a contact finger portion extending in the Y direction away from the vertically-extending contact body portion of 322 a source/drain contact 508 connected to the source/drain regions 114, 114-1, 114-2 (Figs. 1, 2, 7I, 7L).
Bouche shows only one contact finger portion associated with each BPR. As such, it is not clear that each BPR, i.e. each of the claimed “contact body portions” includes a plurality of contact finger portions contacting a respective source/drain region 114.
Kim teaches a semiconductor device, including an array finFETs (Kim: Fig. 1) configured, in plan view, the same as shown in Fig. 3A of Bouche. Like Bouche, Kim teaches a plurality of backside power rails 12, 13 in power rail regions PR1, PR2, respectively (Kim: ¶ 26; e.g. Figs. 1, 2, 8, 9) along respective gate cuts, generally at “gate isolation patterns 80” (Kim: ¶ 27), the gate cuts extending through a plurality of gate electrodes GSN/GSP (Kim: ¶ 27). Kim further teaches that each power rail 12, 13 in each power rail region PR1, PR2 includes a plurality of contact structures 91, 92 including a vertical portion 92v body portion connected to the power rails 12, 13 and a contact finger portion 92a extending horizontally from the vertical portion 92v to contact the source/drain structures SG (Kim: ¶¶ 28, 42; Figs. 1, 2, 8, 9).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include a plurality of contact finger portions (i.e. portion of 322 extending in Y direction from vertical portion of 322 in Figs. 3A, 7I, 7L) extending from each BPR, i.e. each claimed “contact body portion” (i.e. vertical portion of 322 in Figs. 3A, 7I, 7L), in Bouche, in order to form plural contacts between each BPR and a plurality of source/drain regions 114 of selected finFETs, as taught in Kim. As such, Kim provides evidence that including a plurality of contact finger portions extending from a single BPR is obvious duplication of parts. The courts have held that mere duplication of parts has no patentable significance unless a new or unexpected result is produced. See In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960).
This is all of the limitations of claim 1.
Claim 2 and 3 read,
2. (Currently Amended) The integrated circuit device as claimed in claim 1, further comprising
[1] a plurality of gate spacers, each gate spacer of the plurality of gate spacers covering side surfaces of a respective gate electrode of the plurality of gate electrodes,
[2] the respective gate electrode being separated from the contact body portion by the gate spacer.
3. (Original) The integrated circuit device as claimed in claim 2, wherein, according to a top view, each of the plurality of gate spacers completely surrounds its corresponding one among the plurality of gate electrodes.
Although not shown, Bouche states,
[0055] In some embodiments, the gate stack 108 may be surrounded by a dielectric spacer, not specifically shown in FIG. 1. The dielectric spacer may be configured to provide separation between the gate stacks 108 of different FinFETs 100 which may be provided along a single fin (e.g., different FinFETs provided along the fin 104, although FIG. 1 only illustrates one of such FinFETs), as well as between the gate stack 108 and the source/drain contacts disposed on each side of the gate stack 108. …
(Bouche: ¶ 55)
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include a plurality of gate spacers covering all sides, i.e. “surrounding” of the gate electrodes 212 because Bouche suggests including this feature .
This is all of the limitations of claims 2 and 3.
With regard to claims 4-7, Bouche further discloses,
4. (Currently Amended) The integrated circuit device as claimed in claim 1, wherein the contact body portion [i.e. vertical column portion of 322 (Figs. 7I, 7L)] extends downward in a vertical direction from a higher vertical level than a top surface of each of the plurality of source/drain regions 114.
5. (Currently Amended) The integrated circuit device as claimed in claim 4, wherein a bottom surface of the contact body portion [i.e. vertical column portion of 322 (Figs. 7I, 7L)] is at a lower vertical level than a bottom surface of one of the plurality of contact finger portions [i.e. Y extension of 322 (Figs. 7I, 7L) in plurality as taught in Kim (supra)].
6. (Currently Amended) The integrated circuit device as claimed in claim 4, wherein the contact body portion [i.e. vertical column portion of 322 (Figs. 7I, 7L)] extends into the substrate 102.
7. (Currently Amended) The integrated circuit device as claimed in claim 4, wherein the contact body portion [i.e. vertical column portion of 322 (Figs. 7I, 7L)] passes through the substrate 102 and extends to a bottom surface of the substrate 102.
Claim 11 reads,
11. (Currently Amended) An integrated circuit device, comprising:
[1] a substrate including a plurality of device regions extending in a first horizontal direction;
[2a] a plurality of gate structures each including a gate electrode and a gate spacer,
[2b] the plurality of gate structures being on the plurality of device regions and extending in a second horizontal direction that is orthogonal to the first horizontal direction, and
[2c] the gate spacer covering side surfaces of the gate electrode;
[3a] a plurality of source/drain regions between a pair of gate structures adjacent to each other in the first horizontal direction among the plurality of gate structures,
[3b] each of the plurality of source/drain regions being on a portion of a respective one of the plurality of device regions;
[4] a plurality of first gate cut regions, each of the plurality of first gate cut regions cutting the gate electrodes of the plurality of gate structures and extending in the first horizontal direction; and
[5] a plurality of contact structures each separated from the gate electrodes of the plurality of gate structures by the gate spacers,
[6a] the plurality of contact structures each including a contact body portion integrally formed with a plurality of contact finger portions,
[6b] the contact body portion filling a respective one of the plurality of first gate cut regions and extending in the first horizontal direction, and
[6c] each of the plurality of contact finger portions extending in the second horizontal direction from the contact body portion and being connected to a respective one of the plurality of source/drain regions.
Claim 11 is distinguished from claim 1 by features [2c] and [5], directed to the gate spacers which, combined with the gate electrodes, are termed “gate structures”. As such, the gate structures were addressed under claims 2 and 3. As such, all of the limitations of claim 11 have been addressed above under claims 1-3.
Claim 12 reads,
12. (Currently Amended) The integrated circuit device as claimed in claim 11, wherein
[1] a first contact finger portion of the plurality of contact finger portions extends from a first side surface in the second horizontal direction of the contact body portion to a first top surface of a respective one of the plurality of source/drain regions, and
[2] a second contact finger portion extends from a second side surface, opposite the first side surface, in the second horizontal direction of the contact body portion to a second top surface of a second respective one of the plurality of source/drain regions.
Bouche shows in Fig. 7H that a contact finger portion can extend in both directions to contact two gate electrodes 212 but does not show that two different contact finger portions extend from opposite sides of the same contact body portion to contact two different source/drain contacts 508, as required by claim 12. Fig. 7I of Bouche showing only the one contact finger portion, as explained under claim 1.
Fig. 1 of Kim further shows contact finger portions 92a extending from opposite side surfaces of each of the power rails 12, 13 in the respective power rail regions PR1 and PR2 (Kim: Fig. 1, 2).
Thus, in addition to being obvious to include multiple contact finger portions extending from a single power rail, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include contact finger portions extending from opposite side surfaces of the BPRs in Bouche in order to allow electrical connection to source/drain regions of finFETs on opposite sides of the power rail, thereby allowing a single power rail to contact a greater number of source/drain regions than extending from only one side surface.
This is all of the limitations of claim 12.
Claim 13 reads,
13. (Currently Amended) The integrated circuit device as claimed in claim 11, wherein the gate spacer covers opposite side surfaces in the first horizontal direction of the gate electrode and opposite side surfaces in the second horizontal direction of the gate electrode.
See discussion under claims 2 and 3, which applies equally here.
With regard to claim 14, Bouche modified according to Kim further teaches,
14. The integrated circuit device as claimed in claim 11, wherein
[1] a top surface of the contact body portion [vertical column portion of 322 extending from the bottom of the substrate to the 330 in Figs. 3A, 7L of Bouche] is at a same vertical level as a top surface of one of the plurality of contact finger portions [portion of 322 extending in Y direction from vertical portion of 322 in Figs. 3A, 7I, 7L of Bouche, in plurality as taught by Kim], and
[2] a bottom surface of the contact body portion is at a lower vertical level than a bottom surface of one of the plurality of contact finger portions [as shown in Figs. 7I and 7L of Bouche].
With regard to claim 17, Bouche further discloses,
17. (Currently Amended) The integrated circuit device as claimed in claim 11, further comprising:
[1a] at least one second gate cut region 312-1, 312-3 separated from the plurality of first gate cut regions 312-2 [Fig. 3A],
[1b] the at least one second gate cut region 312-1, 312-3 cutting some of the gate electrodes 212 of the plurality of gate structures 212 and extending in the first horizontal direction X; and
[2] an isolation insulating layer 318 filling the at least one second gate cut region 312-1, 312-3.
Although no one of the gate cuts 312-1, 312-3 is shown to cut “some”, i.e. more than one, gate electrode 212, Bouche states, that
[0074] In various embodiments, some of the metal gate cuts 312 may cross only a single metal gate line 212, as is shown in FIG. 3A with the metal gate cuts 312-1 and 312-3 (some other examples of such metal gate cuts are also shown in FIG. 3A but not specifically labeled in order to not clutter the drawing), while other metal gate cuts 312 may cross multiple metal gate lines 212, as is shown in FIG. 3A with the metal gate cut 312-2 …
(Bouche: ¶ 74; emphasis added)
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include a gate cut such as 312-1 or 312-3 that is entirely filled with dielectric 318 to cut more than one gate electrode 212 because Bouche suggests this option, which would allow greater options in the integrated circuit design, as would be readily apparent to one having ordinary skill in the art.
This is all of the limitations of claim 17.
Claim 20 reads,
20. (Currently Amended) The integrated circuit device as claimed in claim 11, further comprising:
[1a] a second gate cut region separated from the plurality of first gate cut regions,
[1b] the second gate cut region cutting some of the gate electrodes of the plurality of gate structures and extending in the first horizontal direction; and
[2] a second isolation insulating layer filling the second gate cut region.
See discussion under claim 17, which applied equally here.
B. Claims 8-10, 15, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Bouche in view of Kim, as applied to claims 4 and 11 above, and further in view of US 2022/0367454 (“Chung”).
Claims 8 and 9 read,
8. (Currently Amended) The integrated circuit device as claimed in claim 4, further comprising
[1] a lower wiring structure below the substrate, the lower wiring structure including a plurality of lower wiring lines, a plurality of lower wiring vias each connected to at least one of the plurality of lower wiring lines, and a lower inter-wiring insulation layer surrounding the plurality of lower wiring lines and the plurality of lower wiring vias,
[2] wherein a source/drain region of the plurality of source/drain regions is electrically connected to at least one of the plurality of lower wiring lines and a respective lower wiring via of the plurality of lower wiring vias through a respective contact structure of the plurality of contact structures.
9. (Currently Amended) The integrated circuit device as claimed in claim 8, further comprising a through electrode extending from a bottom surface of the substrate into the substrate and connecting the contact body portion to at least one of the plurality of lower wiring lines and the plurality of lower wiring vias.
The prior art of Bouche in view of Kim, as explained above, teaches each of the features of claims 1 and 4.
Fig. 3B of Bouche shows that back side power rails, BDV or BPR, are connected to a bottom side metal line BM0. Bouche also shows a front side metallization M0 for, e.g. “routing”. Because the power rails 322 formed in the gate cuts shown in Figs. 5A and 7L of Bouche extend through the substrate 102, the metal BM0, i.e. the claimed “lower wiring layer” if formed below the substrate 102, as required by feature [1] of claim 8.
However, Bouche fails to show the details of either of the lower wiring layer and does not, consequently, teach all of the limitations of claims 8 and 9.
Chung, like Bouche, teaches a finFET array including a plurality of gate electrode 102 over a plurality of fins 55 forming channels and source/drain regions 92 (Chung: Fig. 1; ¶¶ 10-11). Also like Bouche, Chung teaches an upper wiring layer 120 connected to gate electrodes 102 by means of a gate contact 114 (Chung: Figs. 27A and 27C; ¶¶ 81, 84-86), and a lower wiring layer 166 (Chung: ¶¶ 19-21) connected to the top surface of the source/drain regions 92 of the finFETs by a source/drain contact structure 112 including a vertically-extending portion and a horizontally extending portion (as in Bouche) contacting a power rail 36 (Chung: ¶¶ 47, 78) extending through the substrate 50 (Chung: ¶ 15), as shown in Fig. 27B of Chung.
Chung further teaches that the lower wiring layer 166 includes wiring lines 164 and wiring vias 164, stating in this regard,
[0020] The first backside interconnect structure 166 may comprise one or more layers of first conductive features 164 formed in one or more stacked first dielectric layers 162. Each of the stacked first dielectric layers 162 may comprise a dielectric material, …
[0021] The first conductive features 164 may comprise conductive lines and conductive vias interconnecting the layers of conductive lines. The conductive vias may extend through respective ones of the first dielectric layers 162 to provide vertical connections between layers of the conductive lines. …
(Chung: ¶¶ 20-21; emphasis added)
Thus, Chung teaches each of the limitations of claims 8 and 9, generally in Fig. 27A-27C, as follows:
8. (Currently Amended) The integrated circuit device as claimed in claim 4, further comprising
[1] a lower wiring structure 166 below the substrate 50, the lower wiring structure 166 including a plurality of lower wiring lines 164 [id.], a plurality of lower wiring vias 164 [id.] each connected to at least one of the plurality of lower wiring lines 164 [id.], and a lower inter-wiring insulation layer 162 surrounding the plurality of lower wiring lines 164 [id.] and the plurality of lower wiring vias 164 [id.] [as shown in Figs. 27A-27C],
[2] wherein a source/drain region 92 of the plurality of source/drain regions 92 is electrically connected to at least one of the plurality of lower wiring lines 164 [id.] and a respective lower wiring via 164 [id.] of the plurality of lower wiring vias 164 [id.] through a respective contact structure 112 of the plurality of contact structures 112 [as shown in Fig. 27B].
9. (Currently Amended) The integrated circuit device as claimed in claim 8, further comprising a through electrode 36 extending from a bottom surface of the substrate 50 into the substrate 50 and connecting the contact body portion 112 to at least one of the plurality of lower wiring lines 164 [id.] and the plurality of lower wiring vias 164 [id.] [as shown in Fig. 27B].
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to provide a lower wiring structure on the lower substrate surfaces of Bouche having the configuration of Chung because Bouche is merely silent as to the configuration of the lower wiring structure, such that one having ordinary skill in the art would use known configurations suitable for the identical purpose of providing lower wiring structure, to electrically connect the source/drain regions of the finFETs to form an integrated circuit.
This is all of the limitations of claims 8 and 9.
Claim 10 reads,
10. (Currently Amended) The integrated circuit device as claimed in claim 8, further comprising:
[1] an upper wiring structure on the plurality of gate electrodes, the upper wiring structure including a plurality of upper wiring lines, a plurality of upper wiring vias connected to at least one of the plurality of upper wiring lines, and an upper inter-wiring insulation layer surrounding the plurality of upper wiring lines and the plurality of upper wiring vias; and
[2a] a plurality of gate contacts each on a respective one of at least some of the plurality of gate electrodes,
[2b] each of the plurality of gate contacts electrically connecting the respective one of the at least some of the plurality of gate electrodes to a corresponding one of at least some of the plurality of upper wiring lines and a corresponding one of at least some of the plurality of upper wiring vias.
As indicated above, while Bouche shows that the upper wiring structure M0 is above the gate electrode 212, gate in Fig. 3B, Bouche does not show or otherwise state that the gate electrodes 212, gate are electrically connected to the upper wiring structure M0. Thus, Bouche fails to teach all of the limitations of claim 10.
As stated above, Chung also teaches an upper wiring layer 120 connected to gate electrodes 102 by means of a gate contact 114 extending through a gate capping layer 106 (Chung: Figs. 27A and 27C; ¶¶ 81, 84-86). Chung further teaches that the upper wiring layer 120 includes wiring lines 122 connected together by vias and surrounded by dielectric 162, stating in this regard,
[0085] The front-side interconnect structure 120 may comprise one or more layers of second conductive features 122 formed in one or more stacked fourth dielectric layers 124. Each of the stacked fourth dielectric layers 124 may comprise a dielectric material …
[0086] The second conductive features 122 may comprise conductive lines and conductive vias interconnecting the layers of conductive lines. The conductive vias may extend through respective ones of the fourth dielectric layers 124 to provide vertical connections between layers of the conductive lines. …
(Chung: ¶¶ 85-86; emphasis added)
Thus, Chung further teaches all of the limitations of claim 10, generally in Figs. 27A and 27C, as follows:
Claim 10 reads,
10. (Currently Amended) The integrated circuit device as claimed in claim 8, further comprising:
[1a] an upper wiring structure 120 on the plurality of gate electrodes 102, the upper wiring structure 120 including
[1b] a plurality of upper wiring lines 122 [id.],
[1c] a plurality of upper wiring vias 122 [id.] connected to at least one of the plurality of upper wiring lines 122 [id.], and
[1d] an upper inter-wiring insulation layer 124 surrounding the plurality of upper wiring lines 122 [id.] and the plurality of upper wiring vias 122 [id.]; and
[2a] a plurality of gate contacts 114 each on a respective one of at least some of the plurality of gate electrodes 102 [Chung: ¶ 81],
[2b] each of the plurality of gate contacts 114 electrically connecting the respective one of the at least some of the plurality of gate electrodes 102 to a corresponding one of at least some of the plurality of upper wiring lines 122 [id.] and a corresponding one of at least some of the plurality of upper wiring vias 122 [id.].
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to provide an upper wiring structure on the plurality of gate electrodes 212 of Bouche having the configuration of Chung, including the gate contacts 114 of Chung, because Bouche is merely silent as to the configuration of the upper wiring structure and contact to the gate electrodes 212, such that one having ordinary skill in the art would use known configurations suitable for the identical purpose of providing an upper wiring structure to electrically connect the gate electrodes of the finFETs to form an integrated circuit.
This is all of the limitations of claim 10.
Claim 15 reads,
15. (Currently Amended) The integrated circuit device as claimed in claim 11, further comprising:
[1] a lower wiring structure below the substrate; and
[2] an upper wiring structure on the gate electrodes of the plurality of gate structures,
wherein
[3] the plurality of contact structures are electrically connected to the lower wiring structure and
[4] the gate electrodes of the plurality of gate structures are electrically connected to the upper wiring structure.
The prior art of Bouche in view of Kim, as explained above, teaches each of the features of claim 11.
With regard to claim 15, Bouche further discloses,
15. (Currently Amended) The integrated circuit device as claimed in claim 11, further comprising:
[1] a lower wiring structure BM0 below the substrate 102 [Fig. 3B]; and
[2] an upper wiring structure M0 on the gate electrodes 212, gate of the plurality of gate structures [Fig. 3B],
wherein
[3] the plurality of contact structures [322 in Figs. 3A, 7I, 7L] are electrically connected to the lower wiring structure BM0 [as shown in Fig. 3B of Bouche] and
[4] … [not taught] …
With regard to feature [4] of claim 15, again, Bouche does not show or otherwise state that the gate electrodes 212, gate are electrically connected to the upper wiring structure M0 and does not therefore disclose the limitations of feature [4].
As explained above under claim 10, Chung teaches the upper wiring structure 120 connected to the gate electrodes 102 by a gate contact 114 in a gate capping layer 106.
Again, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to provide an upper wiring structure on the plurality of gate electrodes 212 of Bouche having the configuration of Chung, including the gate contacts 114 of Chung, because Bouche is merely silent as to the configuration of the upper wiring structure and contact to the gate electrodes 212, such that one having ordinary skill in the art would use known configurations suitable for the identical purpose of providing an upper wiring structure to electrically connect the gate electrodes of the finFETs to form an integrated circuit.
This is all of the limitations of claim 15.
Claim 16 reads,
16. (Currently Amended) The integrated circuit device as claimed in claim 15, wherein
[1] each of the plurality of contact structures is connected to a respective one of some of the plurality of source/drain regions,
[2a] the integrated circuit device further comprising:
[2b] a contact island connected to at least one other source/drain region and separated from the plurality of contact structures, the contact island extending in the second horizontal direction; and
[2c] a via contact connected to a top of the contact island, the via contact electrically connecting the contact island to the upper wiring structure.
The prior art of Bouche in view of Kim and Jain, as explained above, teaches each of the features of claim 15.
With regard to claim 16, Bouche further discloses,
16. The integrated circuit device as claimed in claim 15, wherein
[1] each of the plurality of contact structures [322 in Figs. 3A, 7L] is connected to a respective one of some of the plurality of source/drain regions 114 [as shown in Fig. 3A, 7I, and 7L],
[2a]-[2c] … [not taught] …
Bouche does not teach the limitations of features [2a]-[2c].
Fig. 1 of Kim further teaches, some contact islands, i.e. the “second contact plug 92b” not connected the back side power rails 12, 13 that extend in the claimed “second horizontal direction, i.e. vertically in the page of Fig. 1 of Beyne which is equivalent to the Y direction in Fig. 3A of Bouche (Kim: Figs. 1, 2; ¶ 42: “A lower surface of the second contact plug 92b may be in contact only with an upper surface of the p-type source/drain layer SG.”).
Thus Kim teaches the limitations of features [2b] of claim 16, as follows:
[2b] a contact island 92b connected to at least one other source/drain region SG and separated from the plurality of contact structures 92a/92v [as shown in Figs. 1 and 2], the contact island 92b extending in the second horizontal direction [as shown in Fig. 1]; and
Chung also teaches all of the limitations of claim 16, generally in Figs. 27B and 27C, as follows:
16. (Currently Amended) The integrated circuit device as claimed in claim 15, wherein
[1] each of the plurality of contact structures 112 is connected to a respective one of some of the plurality of source/drain regions 92,
[2a] the integrated circuit device further comprising:
[2b] a contact island [112 on right side of Fig. 27B connected to the right-side source/drain region 92 Chung: ¶ 81] connected to at least one other source/drain region [right-side source/drain region 92in Fig. 27B] and separated from the plurality of contact structures [i.e. the left-side contact structure 112 connected to the lower wiring structure 166 by the power rail 36 in Fig. 27B], the contact island 112 extending in the second horizontal direction [because it has volume]; and
[2c] a via contact 113 connected to a top of the contact island [112 on right side of Fig. 27B], the via contact 113 electrically connecting the contact island [112 on right side of Fig. 27B] to the upper wiring structure 120 [as shown in Fig. 27C].
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the contact islands of either of Kim and Chung, extending in the claimed “second horizontal direction”, which is the same in both of Kim and Bouche, i.e. the Y direction in Bouche, connected to the upper wiring structure, as taught in Chung, in order to electrically connect selected source/drain regions 114 of Bouche to interconnect other than to the power rail, as taught in each of Kim and Chung, in order to form an integrated circuit.
This is all of the limitations of claim 16.
C. Claims 18 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Bouche in view of Kim and US 2019/0214502 (“Xu”).
Claim 18 reads,
18. (Currently Amended) An integrated circuit device, comprising:
[1] a substrate including a plurality of device regions extending in a first horizontal direction;
[2a] a plurality of gate structures each including a gate electrode, a gate capping layer on the gate electrode, a gate spacer, and a gate insulating film,
[2b] the plurality of gate structures being on the plurality of device regions and extending in a second horizontal direction that is orthogonal to the first horizontal direction,
[2c] the gate spacer covering side surfaces of the gate electrode and surrounding the side surfaces of the gate electrode according to a top view, and
[2d] the gate insulating film being between the gate electrode and the gate spacer;
[3a] a plurality of source/drain regions between a pair of gate structures adjacent to each other in the first horizontal direction among the plurality of gate structures,
[3b] each of the plurality of source/drain regions being on a portion of a respective one of the plurality of device regions;
[4] a plurality of first gate cut regions, each of the plurality of first gate cut regions cutting the plurality of gate structures and extending in the first horizontal direction between a pair of device regions adjacent to each other in the second horizontal direction among the plurality of device regions; and
[5a] a plurality of contact structures separated from the gate electrodes of the plurality of gate structures by the gate spacers,
[5b] the plurality of contact structures each including a contact body portion integrally formed with a plurality of contact finger portions,
[5c] the contact body portion filling a respective one of the plurality of first gate cut regions, extending in the first horizontal direction, and extending into the substrate in a vertical direction, and
[5d] each of the plurality of contact finger portions extending in the second horizontal direction from the contact body portion and being connected to a respective one of the plurality of source/drain regions.
With regard to claim 18, Bouche modified according to Kim to include a plurality of contact finger portions extending from a single BPR, i.e. the claimed “contact body portion”, as explained under claim 1, above, teaches,
18. An integrated circuit device, comprising:
[1] a substrate [102 of Bouche] having a plurality of device regions [e.g. fins 104 of Bouche] extending in a first horizontal direction X [Bouche: Figs. 1, 2, 3A];
[2a] a plurality of gate structures each including a gate electrode [212 of Bouche], … , a gate spacer [¶ 55 of Bouche, as explained under claims 2 and 3 above], and a gate insulating film [included in 430 in Fig. 4D of Bouche (¶ 87)],
[2b] the plurality of gate structures being on the plurality of device regions and extending in a second horizontal direction Y that is orthogonal to the first horizontal direction X [as shown in Figs. 2 and 3A of Bouche],
[2c] the gate spacer [not shown] covering side surfaces of the gate electrode 212 and surrounding the side surfaces of the gate electrode 212 according to a top view [¶ 55 of Bouche; as explained under claims 2 and 3, above], and
[2d] the gate insulating film 430 being between the gate electrode 212 and the gate spacer [as shown in Fig. 4D of Bouche because the gate dielectric 430 runs along the sidewalls 432 of the dielectric 318 of the gate cut dielectric 318 where the surrounding gate spacer would be, if shown, again, as explained under claims 2 and 3];
[3a] a plurality of source/drain regions [114-1, 114-2 of Bouche; Figs. 7I, 7L] between a pair of gate electrodes 212 adjacent to each other in the first horizontal direction X among the plurality of gate electrodes 212 [as shown in Figs. 2 and 7I],
[3b] each of the plurality of source/drain regions 114-1, 114-2 being on a portion of a respective on of the plurality of device regions [as shown in Fig. 2 of Bouche];
[4] a plurality of first gate cut regions [312-2 of Bouche], each of the plurality of first gate cut regions 312-2 cutting the plurality of gate structures and extending in the first horizontal direction X between a pair of device regions 104 adjacent to each other in the second horizontal direction Y among the plurality of device regions 104 [as shown in Figs. 3A and 7I of Bouche and as further explained under claim 1, above]; and
[5a] a plurality of contact structures [322 in Figs. 3A, 7I, 7L of Bouche] separated from the gate electrodes 212 of the plurality of gate structures by the gate spacers [because the gate spacers surround the sidewalls of the gate electrodes 212 again, as explained under claims 2 and 3, above],
[5b] the plurality of contact structures [322 in Figs. 3A, 7I, 7L of Bouche] each including a contact body portion [320 in Figs. 3A, 5A (¶¶ 76, 89) or vertical column portion of 322 extending from the bottom of the substrate to the 330 in Figs. 3A, 7L] integrally formed with a plurality of contact finger portions [i.e. portion of 322 extending in Y direction from vertical portion of 322 in Figs. 3A, 7I, 7L Bouche, made in plurality as taught by Kim, as explained under claim 1, above],
[5c] the contact body portion [i.e. 322 in Figs. 7I, 7L of Bouche] filling a respective one of the plurality of gate cut regions 312-2 [as shown in Fig. 3A, 7I, 7L of Bouche], extending in the first horizontal direction X, and extending into the substrate 102 in a vertical direction [as shown in Fig. 3A, 7I, 7L of Bouche], and
[5d] each of the plurality of contact finger portions [i.e. the Y extension of 322 in Figs. 7I, 7L of Bouche, made in plurality as taught by Kim, as explained under claim 1, above] extending in the second horizontal direction Y from the plurality of contact body portions [i.e. vertical column portion of 322 in Fig. 7I, 7L of Bouche)] and being connected to at least some of the plurality of source/drain regions [114 of Bouche; Figs. 3A, 7I, 7L].
With regard to feature [2a] of claim 18, Bouche only lacks showing “a gate capping layer on the plurality of gate electrodes”.
Xu, like Bouche (e.g. Bouche: ¶¶ 24, 25, 27, 32, 121, 157, 170), teaches a method of making a nanoribbon, gate-all-around, transistor. Xu further teaches using a gate capping layer 144 on the metal gate electrode 143 because “the gate cap 144 is capable of protecting the underlying gate materials during subsequent processing operations” (Xu: ¶ 82, last sentence).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include a gate cap over the gate electrodes 212 in Bouche in order to protect them from subsequent processing, as taught in Xu. As such, Xu may be seen as an improvement to Bouche in this aspect. (See MPEP 2143.)
This is all of the limitations of claim 18.
With regard to claim 19, Bouche further discloses,
19. (Currently Amended) The integrated circuit device as claimed in claim 18, further comprising a first isolation insulating layer [any one or more of gate cut dielectric [318 of Bouche in Figs. 3A, 7I, 7L] covering at least a portion of a side surface in the second horizontal direction of the contact body portion [i.e. vertical column portion of 322 extending from the bottom of the substrate to the 330 in Figs. 3A, 7I, 7L of Bouche].
III. Response to Arguments
Applicant’s arguments filed 08/03/2026 have been fully considered but they are moot because the new grounds of rejection do not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant’s amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
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Signed,
/ERIK KIELIN/
Primary Examiner, Art Unit 2814
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