Prosecution Insights
Last updated: October 04, 2026
Application No. 18/429,625

CHIP-ON-FILM STRUCTURE, DISPLAY DEVICE AND SPLICED DISPLAY DEVICE

Non-Final OA §102§103
Filed
Feb 01, 2024
Priority
Dec 07, 2021 — CN 202111484204.3 +2 more
Examiner
PHAM, THANHHA S
Art Unit
2812
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Xiamen Extremely Pq Display Technology Co. Ltd.
OA Round
1 (Non-Final)
85%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
90%
With Interview

Examiner Intelligence

Grants 85% — above average
85%
Career Allowance Rate
761 granted / 891 resolved
+17.4% vs TC avg
Minimal +5% lift
Without
With
+4.8%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
15 currently pending
Career history
904
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
40.1%
+0.1% vs TC avg
§102
28.1%
-11.9% vs TC avg
§112
24.8%
-15.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 891 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election of species a3 and species b2, claims 1, 3, 5-11, and 13-20 without traverse in the reply filed on 07/01/2026 is acknowledged. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1, 3, 5, 9-11 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by YU et al [US 2022/0367328]. ► With respect to claim 1, YU e al (fig 9) discloses a chip-on-film structure, comprising: a base (500, text [0091]), wherein the base includes a first surface (501) and a second surface (502) oppositely disposed; a first circuit (510, text [0091)) covering the first surface, wherein the first circuit includes a driving chip bonding area (540); a display panel bonding end (550, text [0100]) disposed on the second surface; and a first conductive portion (530, text [0091]) connected to the first circuit and the display panel bonding end respectively. ► With respect to claim 3, YU e al (fig 9) discloses wherein the base further comprises a third surface and a fourth surface, the third surface is connected to the first surface and the second surface, the fourth surface is connected to the first surface and the second surface; and the first conductive portion (530) covers the third surface. ► With respect to claim 5, YU e al (fig 9) discloses wherein the display panel bonding end (550, text [0100]) is spaced apart from the first conductive portion (530, text [0091]) in a target direction, and the target direction is parallel to the second surface; wherein the chip-on-film structure further includes a second circuit (520), the second circuit at least partially covers the second surface, the display panel bonding end is disposed on a side of the second circuit away from the base, and the first conductive portion (530) is connected to the display panel bonding end through the second circuit. ► With respect to claim 9, YU e al (fig 9) discloses wherein the first circuit further comprises a circuit board bonding area (560, text [0101]); and the circuit board bonding area and the display panel bonding end are respectively disposed close to opposite ends of the base (500). ► With respect to claim 10, YU e al (fig 9) discloses wherein the chip-on-film structure further comprises a driving chip (100, text [0100]) and a circuit board (700, text [0101]), the driving chip is disposed in the driving chip bonding area and is connected to the first circuit, and the circuit board is disposed in the circuit board bonding area and is connected to the first circuit. ► With respect to claim 11, YU e al (fig 9) discloses the chip-on-film structure of claim 1 and a display panel (600, text [0100]), wherein the display panel is connected to the display panel bonding end in the chip-on-film structure. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 13 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over YU et al [US 2022/0367328] in view of Yong Fan [CN-215933634] ► With respect to claim 13, Yu et al substantially discloses the claimed chip on film structure but is silent wherein the display panel is a bottom light-emitting display panel; wherein a top of the bottom light-emitting display panel has a first bonding end, the chip-on-film structure is disposed on top of the display panel, and the display panel bonding end faces the display panel and is connected to the first bonding end. However, Yong Fan (fig 1, whole text document) teaches using the display panel the is a bottom light-emitting display panel; wherein the top of the bottom light-emitting display panel has the first bonding end (31), the chip-on-film structure is disposed on top of the display panel, and the display panel bonding end (32) faces the display panel and is connected to the first bonding end. Therefore, it would have been obvious for those skilled in the art to modify the chip -on-film structure of Yu et al by having the display panel bottom light-emitting display panel having the first bonding end arranged as being claimed, per taught by Yon Fan, to provide designed display device as being needed in electronic device. ► With respect to claim 20, using a plurality of display device for spliced display device has been known in the art. The courts have held that mere duplication of parts has no patentable significance unless a new or unexpected result is produced see In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960). Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over YU et al [US 2022/0367328] in view of Yong Fan [CN-215933634] ► With respect to claim 7, Yu et al substantially discloses the chip-on-film structure but does not expressly teach a first protective and the first protective layer is disposed on a side of the first circuit away from the base. However, Lim et al (figs 36 & 37) teaches the first protective layer (410 or 420) on the side of the first circuit (210 or 220) away from the base (100) Therefore, it would have been obvious for those skilled in the art to modify the chip-on-film structure of Yu et al by using the first protective layer as being claimed, per taught by Lim et al, to provide a better reliability chip-on-film structure where cracking generation of the first circuit is prevented. Allowable Subject Matter Claims 6, 8, and 14-19 are objected. ConclusionConclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to THANHHA S PHAM whose telephone number is (571)272-1696. The examiner can normally be reached Monday-Friday. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at 571-270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /THANHHA S PHAM/Primary Examiner, Art Unit 2812
Read full office action

Prosecution Timeline

Feb 01, 2024
Application Filed
Sep 14, 2026
Non-Final Rejection mailed — §102, §103 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
85%
Grant Probability
90%
With Interview (+4.8%)
2y 3m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 891 resolved cases by this examiner. Grant probability derived from career allowance rate.

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