DETAILED ACTION
Response to Arguments
Applicant’s arguments, see page 2 of the remarks, filed on October 27, 2025, with respect to objections to the drawings have been fully considered and are persuasive. The objection of the drawings has been withdrawn.
Applicant’s arguments, see page 2 of the remarks, filed on October 27, 2025, with respect to objections to the specification have been fully considered and are persuasive. The objection of the specification has been withdrawn.
Applicant’s arguments, see pages 2-4 of the remarks, filed on October 27, 2025, with respect to claim objections have been fully considered and are persuasive. The objection of claims 1-8, 11, 13, 15, and 20 has been withdrawn.
Applicant’s arguments, see page 4 of the remarks, filed on October 27, 2025, with respect to rejections under 35 U.S.C. 112(b) have been fully considered and are persuasive. The rejection of claims 6-8 and 15 has been withdrawn.
Drawings
The drawings were received on October 27, 2025. These drawings are acceptable by the examiner.
Claim Objections
Claims 2-4, 7, 10-12, and 15-20 are objected to because of the following informalities:
2. (Proposed Amendment) The communications circuit of claim 1, wherein the series combination of the first resistor and the first capacitor combined with an input resistor of the RX frontend operate as a bandpass filter configured to coincide with a first post cursor output by the RX frontend.
4. (Proposed Amendment) The communications circuit of claim 1, wherein a data rate supported by the RX frontend is higher than 32 gigabits per second.
7. (Proposed Amendment) The communications circuit of claim 6, wherein a resistance of the first and second resistors is matched[[,]] within first device tolerances, and a capacitance of the first and second capacitors is matched within second device tolerances.
10. (Proposed Amendment) The communications device of claim 9, wherein the series combination of the first resistor and the first capacitor is combined with an input resistor of the single-to-differential signal amplifier operate as a bandpass filter configured to coincide with a first post cursor output by the single-to-differential signal amplifier.
12. (Proposed Amendment) The communications device of claim 9, wherein a data rate supported by the RX frontend is higher than 32 gigabits per second.
15. (Proposed Amendment) The communications device of claim 14, wherein a resistance of the first and second resistors is matched[[,]] within first device tolerances, and a capacitance of the first and second capacitors is approximately matched within second device tolerances.
16. (Proposed Amendment) The communications device of claim 14, wherein
the positive differential tap point is located in a first source of a first n-type metal- oxide semiconductor (NMOS) transistor, which is positioned in a positive side of the single-to-differential signal amplifier; and
the negative differential tap point is located in a second source of a second NMOS transistor, which is positioned in a negative side of the single-to-differential signal amplifier.
17. (Proposed Amendment) A method of operating a communications circuit comprising a receiver (RX) frontend including an analog decision feedback equalizer coupled to an RX deserializer
coupling a first feedback loop of the analog decision feedback equalizer directly between a positive output of the RX frontend to a positive differential tap point of an input to a single-to-differential amplifier of the RX frontend; and
coupling a second feedback loop of the analog decision feedback equalizer directly between a negative output of the RX frontend to a negative differential tap point of the input to the single-to-differential amplifier of the RX frontend.
18. (Proposed Amendment) The method of claim 17, wherein the first feedback loop comprises a first inverter and a series combination of a first resistor and a first capacitor coupled in series with the first inverter, and wherein is not sampling the positive output of the RX frontend.
19. (Proposed Amendment) The method of claim 17, wherein the second feedback loop comprises a second inverter and a series combination of a second resistor and a second capacitor coupled in series with the second inverter, and wherein the method further comprises the analog decision feedback equalizer is not sampling the negative output of the RX frontend.
20. (Proposed Amendment) The method of claim 19, further comprising designing the series combination of the second resistor and the second capacitor combined with an input resistor of the single-to-differential amplifier of the RX frontend as a bandpass filter configured [[is]] to coincide with a first post cursor output by the RX frontend.
Claim 3 depends from claim 2, therefore it is also objected.
Claim 11 depends from claim 10, therefore it is also objected.
Claim Rejections - 35 USC § 112
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 18-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Both claims 18 and 19 (lines 3-4) recite “the method further comprises the analog decision feedback equalizer not sampling the negative output of the RX frontend.” However, the claims merely recite used without any active, positive steps delimiting how these uses are actually practice. Without reciting any practice, positive steps, the claims do not achieve the purpose of a method. See the proposed amendments to claims 18 and 19 by the examiner.
Claim 20 depends from claim 19, therefore it is also rejected.
Allowable Subject Matter
The indicated allowability of claims 1, 4, and 5 is withdrawn in view of the newly discovered reference(s) to CHO et al. (US 2021/0288590 A1) and Pavan et al. (US 6.552,615 B1). Rejections based on the newly cited reference(s) follow.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 4, and 5 are rejected under 35 U.S.C. 103 as being unpatentable over CHO et al. (US 2021/0288590 A1), hereinafter “Cho” in view of Pavan et al. (US 6.552,615 B1), hereinafter “Pavan”.
Cho illustrates a receiver 100 in Figure 1 comprising: front-end circuits 102 including a continuous time linear equalizer (CTLE) 106; and digital backend circuits 104. Figures 2-4, 6-9, and 11 disclose alternative embodiments of the CTLE 106 including converters, transistors, and capacitors.
Regarding claim 1, Cho illustrates a communications circuit (receiver 100 in Figure 1) comprising: a receiver (RX) frontend (front-end circuit 102) coupled to an RX deserializer (digital backend circuits 104). Although Cho does not explicitly show or teach that the digital backend circuit 104 is a deserializer, inherently, a digital backend circuit (often called the Physical Coding Sublayer or PCS) typically follows a frontend analog circuit (the Physical Medium Attachment or PMA) in a high-speed deserializer (SerDes) circuit. This structure is considered standard for modern high-speed communications.
However, Cho fails to show or teach that the CTLE 106 is a decision feedback equalizer comprises: a first inverter; and a series combination of a first resistor and a first capacitor coupled in series with the first inverter.
Pavan illustrates an optical receiver 100 in Figure 1 comprising: a photodiode 110; a transimpedance amplifier (TIA) 120, which functions as a I-V- converter; a negative feedback loop 130; an RC circuit 140; an equivalent load RC circuit 160; and a signal path 150. Inherently, the combination of a TIA, an RC circuit (often acting as a channel or analog equalizer), a feedback loop (containing previous symbol decisions), and an equivalent load RC circuit (often used for modeling or impedance matching) can function as a Decision Feedback Equalizer (DFE). In high-speed data links, this configuration acts as a non-linear equalizer that uses past symbol decisions to cancel post-cursor Inter-Symbol Interference (ISI) without amplifying noise.
As shown in Figure 1 and described above, Pavan’s optical receiver 100 comprises a decision feedback equalizer including: a first inverter (I-V-converter 120); and a parallel combination of a first resistor (R1a) and a first capacitor (C1a) coupled in series with the first inverter. Although the first resistor (R1a) and the first capacitor (C1a) are connected in parallel with each other instead coupled in series with each other as recited in claim 1, swapping between series and parallel arrangements of RC circuits is a matter of routine optimization or design choice.
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to modify Cho’s CTLE with Pavan’s DFE circuit to include a first inverter, and a series combination of a first resistor and a first capacitor coupled in series with the first inverter, such as, to modify Pavan’s parallel RC circuit in series to achieve the same result in a different, well-known, and equivalent circuit topology.
Regarding claim 4, although Cho does not explicitly show or teach that a data rate supported by the RF frontends 102 is higher than 32 gigabits per second, it is well known in the art that Cho’s RF frontends 102, particularly those operating in the millimeter-wave (mmWave) bands or using advanced, high-speed data converters, support data rates higher than 32 gigabits per second (Gbps). While 32 Gbps is a significant, high-speed milestone often cited in experimental, research, and specific high-bandwidth applications, it is no longer the upper limit for state-of-the-art RF systems.
Regarding claim 5, although Cho does not explicitly show or teach that Cho’s RF frontends 102 and the digital backend circuits 104 are configured to operate at a supply voltage that is lower than 1.0 volt, it is well known in the art that receiver (RX) frontends and deserializers in high-speed serializer/deserializer (SerDes) systems are configured to operate at supply voltages lower than 1.0 volt. This trend is driven by the scaling of CMOS technologies (e.g., 28-nm, 16-nm, 7-nm, and below), which necessitates lower supply voltages to prevent reliability issues, reduce power consumption, and manage thermal constraints. While 1.8V or 3.3V may be used for older or less speed-critical I/O, the high-speed data path (RX frontend) of modern SerDes, in which the data rate is high, routinely operates below 1.0V.
Allowable Subject Matter
Claims 9, 13, and 14 are allowed.
Claims 6 and 8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 2-3 and 7 would be allowable if rewritten to overcome the objection(s) set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Claims 10-12 and 15-20 would be allowable if rewritten or amended to overcome the objection(s) set forth in this Office action.
Claims 18-20 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Staszewski et al. relates to a multiple signal reception enabled receiver in Figure 5 comprising: a plurality of N front end circuits each comprising an analog RX circuit 54 coupled to an antenna 52 and a dedicated local oscillator (LO) 56; a signal combiner 58; an analog to digital converter (ADC) 60; a digital RX processing block 62; and N digital baseband (DBB) processing blocks 64.
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/Young T. Tse/Primary Examiner, Art Unit 2632