DETAILED ACTION
This action is responsive to the following communication: the response filed 11/13/2025. The changes and remarks disclosed therein have been considered.
Claim(s) status: 1-20 pending.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4, 7-11, 14-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Huang (US 2024/0168643) in view of Leem et al. (US 2015/0019922 ‒hereinafter Leem).
Regarding claim 1, Huang discloses a method comprising;
receiving a request to perform a read operation (“control unit 8023 instructs the memory OF 8022 to read user data and parity from the memory 803 in accordance with a command from the host 804” para 0064) on a multi-bit memory cell (“each memory cell can store one or more bits” para 0066);
for each page of the multi-bit memory cell (i.e. three bits includes upper page, middle page, lower page; para 0075, further “the multiple three-bit memory cells (TLC) coupled to one word line, each memory cell corresponds to a Upper Page (UP), a Middle Page (MP) and a Lower Page (LP)” para 0086), performing a read operation on a respective page of the multi-bit memory cell (any respective UP/MP/LP of the TLC, i.e. reading “the three-bit stored data stored in the memory cell is read by applying seven read voltage levels for distinguishing between the eight voltage ranges. The upper page corresponds to two read voltage levels, the middle page corresponds to three read voltage levels, and the lower page corresponds to two read voltage levels” para 0075);
responsive to determining that the read operation on the respective page failed (“step S901 is executed, obtaining the target read retry table from the set of read retry tables, after the read operation fails” para 0078), determining whether the respective page (i.e. whether the respective page is an affected page) is at least one of either a lower logical page (LP) of the multi-bit memory cell or an upper logical page (UP) of the multi-bit memory cell (determining at least one type of page affected and “obtaining the target read retry table from the read retry tables corresponding to the affected at least one type of page” para 0089);
performing a read error handling operation (read retry operation, i.e. “obtaining, when a read operation of the memory fails, a target read retry table from a set of read retry tables” para 0061) on the respective page (“when the read operation fails due to different problems and the read retry operation is performed, it is only necessary to poll the read retry tables corresponding to one type of page or several types of pages among the lower page/middle page/upper page” para 0087);
obtaining, from the read error handling operation, a read level (“S902: obtaining read retry voltages through the target read retry table” para 0062) associated with a successful read of the respective page (i.e. read retry operation pass in which read is successful; fig. 7); and
responsive to determining that the respective page is the LP or UP (i.e. the cause of failure of the read operation for respective type of page is determined; para 0090), rearranging (i.e. adjusting), based on the obtained read level (i.e. from read retry tables), an ordering of a plurality of entries of a read retry data structure associated with the read error handling operation (“LRU algorithm is used to adjust the order of a plurality of read retry tables corresponding to each type of page” para 0097).
Huang does not expressly disclose a direction of the obtained read level, to prioritize values of the read error handling operation of the same direction.
Leem discloses a direction of the obtained read level (a direction of obtained read reference levels R_01/R_02/R_03 associated with having positive/negative value in an MRR table; fig. 3, 6-8), to prioritize values (i.e. via priority manager; para 0019) of the read error handling operation (i.e. read recover/retry) of the same direction (“[moving read reference] MRR table including a number of prioritized entries used to recover from a reading error” including the read reference levels with the direction; fig. 6-8 para 0030).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Huang is modifiable as taught by Leem for the purpose of improving read error handling schemes by adapting read retry entries with certain priorities to prevent a large number of re-reads (Abstract, para 0003, 0017-0018 of Leem), which predictably benefits the commonly understood advantage of having efficient device operations.
Regarding claim 2, Huang discloses the method, wherein each entry of the plurality of entries comprises a plurality of read levels, and wherein each read level of the plurality of read levels refers to a threshold voltage of the multi-bit memory cell (para 0086).
Regarding claim 3, Huang does not expressly disclose the method, further comprising: performing a subsequent read error handling according to the rearranged ordering of the read retry data structure.
Leem discloses performing a subsequent read error handling (“updated MRR table may then be ready for use to recover from a read error of the one or more memory cells of non-volatile memory 130” para 0074) according to the rearranged ordering (i.e. via order feature 218; fig. 2, para 0073) of the read retry data structure (a moving read reference (MRR) table for recovering from a read error; para 0018).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Huang is modifiable as taught by Leem for the purpose of improving read error handling schemes by adapting read retry entries with certain priorities to prevent a large number of re-reads (Abstract, para 0003, 0017-0018 of Leem), which predictably benefits the commonly understood advantage of having efficient device operations.
Regarding claim 4, Huang discloses the method, wherein the read error handling operation comprises: for each entry of the read retry data structure, performing, using a read level of a plurality of read levels associated with a respective entry, a read operation on the respective page (fig. 9); and determining whether the read operation is successful (i.e. read retry operation pass in which read is successful; fig. 7).
Huang does not expressly disclose determining using the read level of the plurality of read levels, is successful.
Leem discloses determining whether the read operation, using the read level of the plurality of read levels, is successful (1040; fig. 10B).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Huang is modifiable as taught by Leem for the purpose of improving read error handling schemes by adapting read retry entries with certain priorities to prevent a large number of re-reads (Abstract, para 0003, 0017-0018 of Leem), which predictably benefits the commonly understood advantage of having efficient device operations.
Regarding claim 7, Huang does not expressly disclose the method, further comprising: updating the read level of the respective page with the obtained read level.
Leem discloses updating the read level of the respective page with the obtained read level (fig. 6-8).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Huang is modifiable as taught by Leem for the purpose of improving read error handling schemes by adapting read retry entries with certain priorities to prevent a large number of re-reads (Abstract, para 0003, 0017-0018 of Leem), which predictably benefits the commonly understood advantage of having efficient device operations.
Regarding claim 8, Huang discloses a system comprising:
a memory device (803; fig. 8); and
a processing device (CPU; fig. 8), operatively coupled to the memory device, the processing device to perform operations comprising:
receiving a request to perform a read operation (“control unit 8023 instructs the memory OF 8022 to read user data and parity from the memory 803 in accordance with a command from the host 804” para 0064) on a multi-bit memory cell (“each memory cell can store one or more bits” para 0066);
for each page of the multi-bit memory cell (i.e. three bits includes upper page, middle page, lower page; para 0075, further “the multiple three-bit memory cells (TLC) coupled to one word line, each memory cell corresponds to a Upper Page (UP), a Middle Page (MP) and a Lower Page (LP)” para 0086), performing a read operation on a respective page of the multi-bit memory cell (any respective UP/MP/LP of the TLC, i.e. reading “the three-bit stored data stored in the memory cell is read by applying seven read voltage levels for distinguishing between the eight voltage ranges. The upper page corresponds to two read voltage levels, the middle page corresponds to three read voltage levels, and the lower page corresponds to two read voltage levels” para 0075);
responsive to determining that the read operation on the respective page failed (“step S901 is executed, obtaining the target read retry table from the set of read retry tables, after the read operation fails” para 0078), determining whether the respective page (i.e. whether the respective page is an affected page) is at a lower logical page (LP) of the multi-bit memory cell or an upper logical page (UP) of the multi-bit memory cell (determining at least one type of page affected and “obtaining the target read retry table from the read retry tables corresponding to the affected at least one type of page” para 0089);
performing a read error handling operation (read retry operation, i.e. “obtaining, when a read operation of the memory fails, a target read retry table from a set of read retry tables” para 0061) on the respective page (“when the read operation fails due to different problems and the read retry operation is performed, it is only necessary to poll the read retry tables corresponding to one type of page or several types of pages among the lower page/middle page/upper page” para 0087);
obtaining, from the read error handling operation, a read level (“S902: obtaining read retry voltages through the target read retry table” para 0062) associated with a successful read of the respective page (i.e. read retry operation pass in which read is successful; fig. 7); and
responsive to determining that the respective page is the LP or UP (i.e. the cause of failure of the read operation for respective type of page is determined; para 0090), rearranging (i.e. adjusting), based on the obtained read level (i.e. from read retry tables), an ordering of a plurality of entries of a read retry data structure associated with the read error handling operation (“LRU algorithm is used to adjust the order of a plurality of read retry tables corresponding to each type of page” para 0097).
Huang does not expressly disclose a direction of the obtained read level, to prioritize values of the read error handling operation of the same direction.
Leem discloses a direction of the obtained read level (a direction of obtained read reference levels R_01/R_02/R_03 associated with having positive/negative value in an MRR table; fig. 3, 6-8), to prioritize values (i.e. via priority manager; para 0019) of the read error handling operation (i.e. read recover/retry) of the same direction (“[moving read reference] MRR table including a number of prioritized entries used to recover from a reading error” including the read reference levels with the direction; fig. 6-8 para 0030).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Huang is modifiable as taught by Leem for the purpose of improving read error handling schemes by adapting read retry entries with certain priorities to prevent a large number of re-reads (Abstract, para 0003, 0017-0018 of Leem), which predictably benefits the commonly understood advantage of having efficient device operations.
Regarding claim 9, Huang discloses the system, wherein each entry of the plurality of entries comprises a plurality of read levels, and wherein each read level of the plurality of read levels reads a page of the multi-bit memory cell (para 0086).
Regarding claim 10, Huang does not expressly disclose the system, wherein the processing device to perform operations further comprising: performing a subsequent read error handling according to the rearranged ordering of the read retry data structure.
Leem discloses performing a subsequent read error handling (“updated MRR table may then be ready for use to recover from a read error of the one or more memory cells of non-volatile memory 130” para 0074) according to the rearranged ordering (i.e. via order feature 218; fig. 2, para 0073) of the read retry data structure (a moving read reference (MRR) table for recovering from a read error; para 0018).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Huang is modifiable as taught by Leem for the purpose of improving read error handling schemes by adapting read retry entries with certain priorities to prevent a large number of re-reads (Abstract, para 0003, 0017-0018 of Leem), which predictably benefits the commonly understood advantage of having efficient device operations.
Regarding claim 11, Huang discloses the system, wherein the read error handling operation comprises: for each entry of the read retry data structure, performing, using a read level of a plurality of read levels associated with a respective entry, a read operation on the respective page (fig. 9); and determining whether the read operation is successful (i.e. read retry operation pass in which read is successful; fig. 7).
Huang does not expressly disclose determining using the read level of the plurality of read levels, is successful.
Leem discloses determining whether the read operation, using the read level of the plurality of read levels, is successful (1040; fig. 10B).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Huang is modifiable as taught by Leem for the purpose of improving read error handling schemes by adapting read retry entries with certain priorities to prevent a large number of re-reads (Abstract, para 0003, 0017-0018 of Leem), which predictably benefits the commonly understood advantage of having efficient device operations.
Regarding claim 14, Huang does not expressly disclose the system, wherein the processing device to perform operations further comprising: updating the read level of the respective page with the obtained read level.
Leem discloses updating the read level of the respective page with the obtained read level (fig. 6-8).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Huang is modifiable as taught by Leem for the purpose of improving read error handling schemes by adapting read retry entries with certain priorities to prevent a large number of re-reads (Abstract, para 0003, 0017-0018 of Leem), which predictably benefits the commonly understood advantage of having efficient device operations.
Regarding claim 15, Huang discloses a non-transitory computer readable storage medium including instructions that, when executed by a processing device (CPU; fig. 8), cause the processing device to perform a method comprising:
receiving a request to perform a read operation (“control unit 8023 instructs the memory OF 8022 to read user data and parity from the memory 803 in accordance with a command from the host 804” para 0064) on a multi-bit memory cell (“each memory cell can store one or more bits” para 0066);
for each page of the multi-bit memory cell (i.e. three bits includes upper page, middle page, lower page; para 0075, further “the multiple three-bit memory cells (TLC) coupled to one word line, each memory cell corresponds to a Upper Page (UP), a Middle Page (MP) and a Lower Page (LP)” para 0086), performing a read operation on a respective page of the multi-bit memory cell (any respective UP/MP/LP of the TLC, i.e. reading “the three-bit stored data stored in the memory cell is read by applying seven read voltage levels for distinguishing between the eight voltage ranges. The upper page corresponds to two read voltage levels, the middle page corresponds to three read voltage levels, and the lower page corresponds to two read voltage levels” para 0075);
responsive to determining that the read operation on the respective page failed (“step S901 is executed, obtaining the target read retry table from the set of read retry tables, after the read operation fails” para 0078), determining whether the respective page (i.e. whether the respective page is an affected page) is a lower logical page (LP) of the multi-bit memory cell or an upper logical page (UP) of the multi-bit memory cell (determining at least one type of page affected and “obtaining the target read retry table from the read retry tables corresponding to the affected at least one type of page” para 0089);
performing a read error handling operation (read retry operation, i.e. “obtaining, when a read operation of the memory fails, a target read retry table from a set of read retry tables” para 0061) on the respective page (“when the read operation fails due to different problems and the read retry operation is performed, it is only necessary to poll the read retry tables corresponding to one type of page or several types of pages among the lower page/middle page/upper page” para 0087);
obtaining, from the read error handling operation, a read level (“S902: obtaining read retry voltages through the target read retry table” para 0062) associated with a successful read of the respective page (i.e. read retry operation pass in which read is successful; fig. 7); and
responsive to determining that the respective page is the LP or UP (i.e. the cause of failure of the read operation for respective type of page is determined; para 0090), rearranging (i.e. adjusting), based on the obtained read level (i.e. from read retry tables), an ordering of a plurality of entries of a read retry data structure associated with the read error handling operation (“LRU algorithm is used to adjust the order of a plurality of read retry tables corresponding to each type of page” para 0097).
Huang does not expressly disclose a direction of the obtained read level, to prioritize values of the read error handling operation of the same direction.
Leem discloses a direction of the obtained read level (a direction of obtained read reference levels R_01/R_02/R_03 associated with having positive/negative value in an MRR table; fig. 3, 6-8), to prioritize values (i.e. via priority manager; para 0019) of the read error handling operation (i.e. read recover/retry) of the same direction (“[moving read reference] MRR table including a number of prioritized entries used to recover from a reading error” including the read reference levels with the direction; fig. 6-8 para 0030).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Huang is modifiable as taught by Leem for the purpose of improving read error handling schemes by adapting read retry entries with certain priorities to prevent a large number of re-reads (Abstract, para 0003, 0017-0018 of Leem), which predictably benefits the commonly understood advantage of having efficient device operations.
Regarding claim 16, Huang discloses the non-transitory computer readable storage medium, wherein each entry of the plurality of entries comprises a plurality of read levels, and wherein each read level of the plurality of read levels reads a page of the multi-bit memory cell (para 0086).
Regarding claim 17, Huang does not expressly disclose the non-transitory computer readable storage medium, wherein the method further comprising: performing a subsequent read error handling according to the rearranged ordering of the read retry data structure.
Leem discloses performing a subsequent read error handling (“updated MRR table may then be ready for use to recover from a read error of the one or more memory cells of non-volatile memory 130” para 0074) according to the rearranged ordering (i.e. via order feature 218; fig. 2, para 0073) of the read retry data structure (a moving read reference (MRR) table for recovering from a read error; para 0018).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Huang is modifiable as taught by Leem for the purpose of improving read error handling schemes by adapting read retry entries with certain priorities to prevent a large number of re-reads (Abstract, para 0003, 0017-0018 of Leem), which predictably benefits the commonly understood advantage of having efficient device operations.
Regarding claim 18, Huang discloses the non-transitory computer readable storage medium, wherein the read error handling operation comprises: for each entry of the read retry data structure, performing, using a read level of a plurality of read levels associated with a respective entry, a read operation on the respective page (fig. 9); and determining whether the read operation is successful (i.e. read retry operation pass in which read is successful; fig. 7).
Huang does not expressly disclose determining using the read level of the plurality of read levels, is successful.
Leem discloses determining whether the read operation, using the read level of the plurality of read levels, is successful (1040; fig. 10B).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Huang is modifiable as taught by Leem for the purpose of improving read error handling schemes by adapting read retry entries with certain priorities to prevent a large number of re-reads (Abstract, para 0003, 0017-0018 of Leem), which predictably benefits the commonly understood advantage of having efficient device operations.
Allowable Subject Matter
Claim(s) 5-6, 12-13, 19-20 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The prior art of record and considered pertinent to the applicant's disclosure does not teach or suggest the claimed invention having the following limitation, in combination with the remaining claimed limitations.
With respect to dependent claim 5, 12, 19, the prior art fails to teach or suggest the claimed limitations, namely responsive to determining that the obtained read level is a negative value, arranging the entries of the read retry data structure with negative values before the entries of the read retry data structure with positive values.
With respect to dependent claim 6, 13, 20, the prior art fails to teach or suggest the claimed limitations, namely responsive to determining that the obtained read level is a positive value, arranging the entries of the read retry data structure with positive values before the entries of the read retry data structure with negative values.
The allowable claims are supported in at least fig. 3 of the instant application.
Response to Arguments
Applicant’s arguments with respect to the pending claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to UYEN SMET whose telephone number is (571) 272-2267. The examiner can normally be reached M-F, 9 AM-5 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard Elms can be reached on (571) 272-1869. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/UYEN SMET/
Primary Examiner, Art Unit 2824______
Prosecution Insights