The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Election/Restrictions
Applicants’ election without traverse of the embodiment of figure 12B in the reply filed on 08/17/2026 is acknowledged.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7, 10-16 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Li et al. (12,598,789). Scheiper et al. (8,241,977).Regarding claims 1 and 12, Li et al. teach in figures 40, 41 and related text a semiconductor structure comprising:
a first transistor (of figure 40) having a first channel length 106 and comprising a first gate structure 144 and a first source/drain region 140 located on each side of the first gate structure;
a first backside source/drain contact placeholder structure 136 of a first depth located beneath, and in contact with, one of the first source/drain regions of the first transistor;
a second transistor (of figure 41) having a second channel length 106 and comprising a second gate structure 144 and a second source/drain region 140 located on each side of the second gate structure; and
a second backside source/drain contact placeholder structure 134 of a second depth located beneath, and in contact with, one of the second source/drain regions of the second transistor,
wherein the second depth (of element 134) is less than the first depth (of element 136).
Li et al. do not explicitly state that the second depth is less than the first depth and do not teach that the second channel length is greater than the first channel length.
Li et al. teach in figures 40 and 41 that the second depth is less than the first depth.
Scheiper et al. teach in related text that “the usage of high speed transistor elements having an extremely short channel may preferably be restricted to high speed signal paths, whereas transistor elements with a longer channel may be used for less critical circuit portions, such as storage transistor elements”.
Scheiper et al. and Li et al. are analogous art because they are directed to channel regions length of semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Tanno because they are from the same field of endeavor.It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form the second depth less than the first depth and to form the second channel length greater than the first channel length, as taught by Scheiper et al., in Li et al.’s device, in order to expand the device capability by being able to use the device more effectively in applications which require specific transistors.
Regarding claims 2 and 12, Li et al. and Scheiper et al. teach substantially the entire claimed structure, as applied to the claims above, including the first backside source/drain contact structure has a first backside source/drain contact placeholder structure width, and the second backside source/drain contact structure has a second backside source/drain contact placeholder structure width.
Li et al. and Scheiper et al. do not teach that the second backside source/drain contact placeholder structure width is greater than the first backside source/drain contact structure width.
Li et al. teach in figures 40 and 41 that the second backside source/drain contact placeholder structure width is greater than the first backside source/drain contact structure width.
It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form the second backside source/drain contact placeholder structure width is greater than the first backside source/drain contact structure width in Li et al.’s device, in order to form the device as intended by Li et al.
Regarding claims 3 and 12, Li et al. and Scheiper et al. teach substantially the entire claimed structure, as applied to the claims above, including the first backside source/drain contact placeholder structure has a first volume and the second backside source/drain contact placeholder structure has a second volume.
Li et al. and Scheiper et al. do not explicitly state that the first volume is substantially equal to the second volume. It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form the first volume is substantially equal to the second volume in Li et al.’s device, in order to adjust the device characteristics according to the requirements of the application in hand.
Regarding claims 4 and 13, Li et al. teach in figures 40, 41 and related text that the first backside source/drain contact placeholder structure is in direct contact with the first source/drain region of the first transistor, and the second backside source/drain contact placeholder structure is in direct contact with the second source/drain region of the second transistor.
Regarding claims 5 and 14, the formation of a first semiconductor buffer layer located between the first backside source/drain contact placeholder structure and the first source/drain region of the first transistor, and a second semiconductor buffer layer located between the second backside source/drain contact placeholder structure and the second source/drain region of the second transistor, is a process limitation because applicants do not distinguish between the first semiconductor buffer layer located and the first backside source/drain contact placeholder structure and the first source/drain region of the first transistor, and between the second semiconductor buffer layer located between the second backside source/drain contact placeholder structure and the second source/drain region of the second transistor.
The formation of two identical layers does not produce a structure which is different from a structure which is formed using only one layer.
Regarding claims 6 and 15, Li et al. teach in figures 40, 41 and related text a first backside source/drain contact structure contacting (at least electrically contacting) the other first source/drain region of the first transistor.
Regarding claims 7 and 16, Li et al. teach in figures 40, 41 and related text a backside interconnect structure 160 electrically connected to the first backside source/drain contact structure by a first backside power rail.
Regarding claims 10 and 19, Li et al. teach in figures 40, 41 and related text a first frontside source/drain contact structure 146 contacting the first source/drain region that contacts the first backside source/drain contact placeholder structure, and a second frontside source/drain contact structure 146 contacting the second source/drain region that contacts the second backside source/drain contact placeholder structure.
Regarding claims 11 and 20, Li et al. teach in figures 40, 41 and related text a frontside back-end-of-the-line (BEOL) interconnect structure 148 contacting the first frontside source/drain contact structure and the second frontside source/drain contact structure.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ORI NADAV whose telephone number is 571-272-1660. The examiner can normally be reached between the hours of 7 AM to 4 PM (Eastern Standard Time) Monday through Friday.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached on 571-272-1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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O.N. /ORI NADAV/
8/29/2026 PRIMARY EXAMINER
TECHNOLOGY CENTER 2800
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