Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
The amendments filed on 5/18/2026 have been fully considered and made of record in this application.
Response to Arguments
Applicant’s arguments with respect to claims 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 9, and 10 are rejected under 35 U.S.C. 102(a)(1) as being clearly anticipated by Sato et al. (US 2018/0182700).
With respect to Claims 1 and 10, Sato teaches an interposer 2C, WL1- WL6, SR1, SR2, IL12, IL23, IL45, IL56 having a first surface as a mounting surface and a second surface 2b for mounting an object MB (i.e. a coreless substrate). The second surface being opposite to the first surface, the interposer comprising a first component 3, 1X exposed directly on the second surface or connected to the second surface 2a via a conductor V23. The first component 3 being included inside the interposer 2C, WL1- WL6, SR1, SR2, IL12, IL23, IL45, IL56 and located at a position closer to the second surface 2a than to the first surface 2b. A sealing resin layer (i.e. epoxy resin) sealing the first component 3. A columnar conductor 2TW electrically connecting s surface of the first component facing the first surface and the first surface. The columnar conductor 2TW being made of a uniform material filling a vertical hole (see paragraphs 25-33, 48, and 53-56; Figs. 5, 9, 29, 30, and 32).
With respect to Claim 2 and 3, Sato teaches a second component 3 (i.e.
capacitor) included inside the sealing resin layer. A first electrode 31a to be
connected to a third component 1X included in the object. A second electrode
to be connected to a fourth component included in the object are arranged
on a surface of the second component closer to the second surface. The second
component is connected to both the first electrode and the second electrode (see Figs.
5, 7, 9, 29, and 32).
With respect to Claim 9 Ogawa discloses the first component 1Y is a capacitor (see paragraph 48).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 7, 8, 10, 17, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Sato et al. (US 2018/0182700) as applied to claim 1 above, and further in view of Ogawa et al. (US 2005/0258548).
With respect to Claims 7 and 17, Sato discloses the claimed invention except
for on the first surface, a first-surface-side outer resin layer is arranged so as to
cover the sealing resin layer, and a first-surface-side wiring layer is arranged between
the first-surface-side outer resin layer and the sealing resin layer, and electrical
connection from the first component to the first surface is made via the first-surface-side
wiring layer.
However, Ogawa discloses on the first surface, a first-surface-side outer resin
layer 140 is arranged so as to cover the sealing resin layer 140. A first-surface-side
wiring layer 144 is arranged between the first-surface-side outer resin layer and the
sealing resin layer. An electrical connection from the first component 130 to the first
surface is made via the first-surface-side wiring layer 144 (see paragraphs 112-116;
Figs. 1 and 10). Thus, Sato and Ogawa have substantially the same environment of
semiconductor enclosed by a resin material of an interposer and closer to the second
surface of the interposer. Therefore, one skilled in the art before the effective filing date
of the claimed invention to incorporate a resin layer with a wiring layer on the first
surface of the interposer of Meyer, since the wiring layer would facilitate electrically
connecting electronic component to a motherboard as taught by Ogawa.
With respect to Claims 8 and 18, Ogawa discloses on the second surface, a
second-surface-side outer resin layer 150 is arranged so as to cover the sealing resin
layer 140. A second-surface-side wiring layer 143 is arranged between the second-
surface-side outer resin layer and the sealing resin layer. Electrical connection is from
the first component 130 to the second surface is made via the second-surface-side
wiring layer (see Figs. 1 and 10).
Allowable Subject Matter
9. Claims 4-6, 11-16, 19, and 20 are objected to as being dependent upon a
rejected base claim, but would be allowable if rewritten in independent form including all
of the limitations of -3the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowance subject
matter: none of the prior art of record teaches or suggest the combination of the
second component is exposed on the first surface in claim 4.
The prior art made of record and not relied upon is cited primarily to show the
product of the instant invention.
Conclusion
10. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning the communication or earlier communications from the
examiner should be directed to Alonzo Chambliss whose telephone number is (571)
272-1927.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's
supervisor, Jacob Y. Choi can be reached on (469) 295-9060. The fax phone number
for the organization where this application or proceeding is assigned is (571) 273-8300.
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AC/July 15, 2026 /Alonzo Chambliss/
Primary Examiner, Art Unit 2897
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