DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, Species B (Fig. 18, claims 1-7) in the reply filed on 7/30/26 is acknowledged.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1 is/are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication No. 2021/0126123 (SCHÖNER) in view of U.S. Patent Application Publication No. 2019/0067424 (KUDOU).
SCHÖNER discloses
A semiconductor device comprising:
a silicon carbide epitaxial layer 3 having:
a p-type buried layer 4; and
a junction field effect region 7b in contact with the p-type buried layer 4 in a gate region G;
a gate oxide layer 10 on the silicon carbide epitaxial layer 3;
a layer 11 on the gate oxide layer 10;
an interlayer dielectric layer 12 on the layer 11.
SCHÖNER fails to disclose
a poly silicon layer;
a first recess formed in the silicon carbide epitaxial layer by passing through the interlayer dielectric layer, the poly silicon layer and the gate oxide layer in a source region; and
a second recess formed in the poly silicon layer in the gate region, wherein a bottom surface of the second recess is higher than a top surface of the gate oxide layer.
KUDOU teaches
A semiconductor device comprising:
a poly silicon layer 108 on gate oxide layer 107a;
a first recess 131 formed in the silicon carbide epitaxial layer 102 by passing through the interlayer dielectric layer 111, the poly silicon layer 108 and the gate oxide layer 107a in a source region 104; and
a second recess 132 formed in the poly silicon layer 108 in the gate region 108g, wherein a bottom surface of the second recess 132 is higher than a top surface of the gate oxide layer 107a.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide a poly silicon layer and a second recess having a bottom surface higher than a top surface of the gate oxide layer in SCHÖNER. The motivation would be to improve reliability and the gate contact structure by reducing resistance and metal diffusion as taught by Kudou ([0044], [0045], [0085]-[0087]).
Claim(s) 2, 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over SCHÖNER in view of Kudou as applied to claim 1 above, and further in view of U.S. Patent Application Publication No. 2018/0182886 (KOBAYASHI).
SCHÖNER discloses
2. The semiconductor device of claim 1, wherein the silicon carbide epitaxial layer 3 further having:
a p-type well region 6 above the p-type buried layer 4;
The combination of references fails to teach
a heavily doped n-type region on a surface of the p-type well region; and
a first heavily doped p-type region below the heavily doped n-type region and within the p-type well region, wherein a depth of the first recess exceeds a depth of the heavily doped n-type region.
KOBAYASHI teaches
A semiconductor device comprising:
a heavily doped n-type region 4 on a surface of the p-type well region 3 / 21; and
a first heavily doped p-type region 22 below the heavily doped n-type region 4 and within the p-type well region 3, wherein a depth of the first recess 8 exceeds a depth of the heavily doped n-type region 4.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide a depth of the first recess that exceeds a depth of the heavily doped n-type region in the modified device of SCHÖNER. The motivation would be to reduce source contact resistance while maintaining breakdown voltage and suppressing punch-through as taught by Kobayashi ([0030], [0031], [0055]).
KUDOU teaches
4. The semiconductor device of claim 2, further comprising:
a first metal layer 112 within the first recess 131 and in contact with the first heavily doped p-type region 105 and the heavily doped n-type region 104 through silicide 109.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide a first metal layer within the first recess and in contact with the first heavily doped p-type region and the heavily doped n-type region through silicide in SCHÖNER. The motivation would be to reduce contact resistance between the source metal and the highly doped n-type and p-type semiconductor regions to thereby improve electrical performance as taught by Kudou ([0044], [0045], [0085]-[0087]).
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over SCHÖNER in view of Kudou as applied to claim 1 above, and further in view of U.S. Patent No. 6,235,593 (Huang) and 8,674,439 (Sdrulla).
The combination of references fails to teach
3. The semiconductor device of claim 1, further comprising:
a contact spacer on the gate oxide layer and in contact with the interlayer dielectric layer and the poly silicon layer; and
an island-shaped oxide layer on the junction field effect region, wherein a thickness of the island-shaped oxide layer is greater than a thickness of the gate oxide layer.
Huang teaches
A semiconductor device comprising:
a contact spacer 34A on the gate oxide layer 22 and in contact with the interlayer dielectric layer 36 and the poly silicon layer 24.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention provide a contact spacer on the gate oxide layer and in contact with the interlayer dielectric layer and the poly silicon layer in the modified device of SCHÖNER. The motivation would be to improve insulation integrity between the source contact and the adjacent polysilicon gate and to permit a more closely spaced self-aligned contact structure as taught by Huang (Summary, Benefits).
Sdrulla teaches
A semiconductor device comprising:
an island-shaped oxide layer 29 on the junction field effect region (between p-body regions), wherein a thickness of the island-shaped oxide layer 29 is greater than a thickness of the gate oxide layer 28 column 7, lines 25-34).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention provide a thickness of the island-shaped oxide layer is greater than a thickness of the gate oxide layer in the modified device of SCHÖNER. The motivation would be to reduce gate-drain capacitance and suppress electric-field stress in the JFET region without thickening the channel oxide, thereby improving switching performance as taught by Sdrulla (Background, Summary, column 5, lines 30-67).
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over SCHÖNER in view of Kudou and Kobayashi as applied to claim 4 above, and further in view of Huang.
Huang teaches
5. The semiconductor device of claim 4, wherein the first metal layer 54 is further disposed on the interlayer dielectric layer 36 and the contact spacer 34A and in contact with the interlayer dielectric layer 36 and the contact spacer 34A.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to configure the source metal / contact to extend over and contact the ILD and dielectric contact spacer in the modified device of SCHÖNER. The motivation would be to provide a self-aligned contact structure with improved insulation between source contact and adjacent gate structure and to permit reduced spacing between neighboring gate and contact structures as taught by Huang (Summary, Benefits).
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over SCHÖNER in view of Kudou and Kobayashi as applied to claim 4 above, and further in view of U.S. Patent Application Publication No. 2015/0137273 (ZHANG).
The combination of references fails to teach
6. The semiconductor device of claim 4, wherein the interlayer dielectric layer is further disposed within the second recess, and the first metal layer within the second recess is not in contact with the poly silicon layer.
ZHANG teaches
A semiconductor device comprising:
wherein the interlayer dielectric layer 209 is further disposed within the second recess 233, and the first metal layer 235 within the second recess 233 is not in contact with the poly silicon layer 217.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to dispose dielectric material within the gate-side recess in the modified device of SCHÖNER. The motivation would be to separate the overlying source / contact metal from the poly silicon gate to prevent contact-to-gate short circuits and improve electrical isolation as taught by ZHANG ([0006], [0032]).
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over SCHÖNER in view of Kudou as applied to claim 1 above, and further in view of WO Publication No. 2016/114055 (KUMAGAI), cited by Applicant.
The combination of references fails to teach
7. The semiconductor device of claim 1, further comprising:
a silicon carbide substrate under the silicon carbide epitaxial layer; and
a second metal layer under the silicon carbide substrate.
KUMAGAI teaches
A semiconductor device comprising:
a silicon carbide substrate 101 under the silicon carbide epitaxial layer 102; and
a second metal layer 113 under the silicon carbide substrate 101.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide a silicon carbide substrate and a second metal layer in the modified device of SCHÖNER. The motivation would be to provide a vertical current path from the source-side device structure through the SiC epi layer and substrate to a backside drain contact as well-known in the vertical SiC power FET art as taught by KUMAGAI. See MPEP 2144.03.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. U.S. Patent No. 6,791,143 (Baliga), U.S. Patent Application Publication Nos. 2023/0307497 (LIU), 2022/0320295 (NGWENDSON), 2015/0372094 (HORII) teach a silicon carbide power transistor structure.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TERESA M ARROYO whose telephone number is (703)756-1576. The examiner can normally be reached Monday - Friday (8:30 A.M. E.T. - 5:00 P.M. E.T.).
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/TERESA M. ARROYO/ Primary Examiner, Art Unit 2893
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