DETAILED ACTION
This Office Action is in response to the Preliminary Amendment filed on February 1, 2024.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 6-10, 12-14, and 16-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shen et al. (CN114171520 A).
In re claim 1, Shen et al. shows (figs. 2, 3, 4) a three-dimensional (3D) ferroelectric random access memory (FeRAM) comprising: a substrate(110); semiconductor patterns (AP) stacked in a vertical direction (Z) on the substrate in a multilayer structure with insulating layers (IL) therebetween, and spaced apart from each other in a first horizontal direction (Y); bit lines (BL) on first side surfaces of the semiconductor patterns in a second horizontal direction (X) , wherein the second horizontal direction is perpendicular to the first horizontal direction, and the bit lines extend in the first horizontal direction (Y) and are spaced apart from each other in the vertical direction (Z); first electrodes (LE) on second side surfaces of the semiconductor patterns in the second horizontal direction, wherein the first electrodes are spaced apart from each other in both the vertical direction and the first horizontal direction; a ferroelectric layer (DL) on the first electrodes in the second horizontal direction, wherein the ferroelectric layer extends in the first horizontal direction; second electrodes (UE) on the ferroelectric layer in the second horizontal direction, wherein the second electrodes extend in the first horizontal direction and are spaced apart from each other in the vertical direction; and word lines (WL, 130A1, 130A2) between two adjacent semiconductor patterns among the semiconductor patterns in the first horizontal direction, wherein the word lines extend in the vertical direction (Z).
In re claim 2, Shen et al. shows (figs. 2, 3, 4) wherein each of the first electrodes has a ‘ Է ' shape on each of a horizontal cross-section perpendicular to the vertical direction and a vertical cross-section perpendicular to the first horizontal direction.
In re claim 3, Shen et al. shows (figs. 2, 3, 4) wherein the ferroelectric layer extends in the vertical direction and comprises a ‘ Է ' -shaped portion along each of the horizontal cross- section and the vertical cross-section, in correspondence to the ‘ Է ' shape of each of the first electrodes.
In re claim 4, Shen et al. shows (figs. 2, 3, 4) wherein each of the second electrodes (UE) comprises: an extension extending in the first horizontal direction on the horizontal cross-section; and a protrusion protruding in the second horizontal direction from the extension in correspondence the ‘ Է ' shape of the ferroelectric layer on the horizontal cross-section and has a rectangular shape filling a ‘ Է ' -shaped inside of the ferroelectric layer on the vertical cross-section.
In re claim 6, Shen et al. shows (figs. 2, 3, 4) wherein each of the first electrodes (UE) 5 has a rectangular shape on both a horizontal cross-section perpendicular to the vertical direction and a vertical cross-section perpendicular to the first horizontal direction. (see the X-axis views in figures 2 and 3).
In re claim 7, Shen et al. shows (figs. 2, 3, 4) wherein the ferroelectric layer (DL) comprises a plurality of ferroelectric layers which are spaced apart from each other in the vertical direction, and wherein each of the plurality of ferroelectric layers comprises: an extension extending in the first horizontal direction; and a protrusion protruding in the second horizontal direction from the extension and contacting each of the first electrodes, wherein the protrusion has a ‘ Է ' shape.
In re claim 8, Shen et al. shows (figs. 2, 3, 4) wherein each of the second electrodes (UE) has a straight band shape extending in the first horizontal direction on the horizontal cross-section and a rectangular shape extending into a ‘ Է ' -shape of each of the plurality of ferroelectric layers.
In re claim 9, Shen et al. shows (figs. 2, 3, 4) wherein one (130A1) or two (130A2) of the word lines are between two of the semiconductor patterns (CH).
In re claim 10, Shen et al. shows (figs. 2, 3, 4) the ferroelectric layer comprises a Hf-based oxide film and at least one dopant of Zr, Si, Al, Y, Gd, La, Sc, and Sr (paragraphs are not labeled-see the translated excerpts pertaining to the dielectric layer (DL).
(Translation portion)
The capacitor dielectric layer DL may be formed of a high-k dielectric material having a higher dielectric constant than that of the silicon oxide or ferroelectric material. In one embodiment, the capacitor dielectric layer DL may be composed of hafnium oxide (HfO), hafnium silicate (HfSiO), hafnium oxynitride (HfON), hafnium silicon oxynitride (HfSiON), lanthanum oxide (LaO), lanthanum aluminum oxide (LaAlO), zirconium oxide (ZrO), zirconium silicate (ZrSiO), zirconium oxynitride (ZrON), zirconium oxynitride (ZrSiON), tantalum oxide (TaO), titanium oxide (TiO), barium strontium titanium oxide (BaSrTiO), barium titanium oxide (BaTiO), lead zirconate titanate (PZT), strontium bismuth tantalate (STB), bismuth iron oxide (BFO), strontium titanium oxide (SrTiO), yttrium oxide (YO), aluminium oxide (Al2O3) or lead scandium tantalum oxide (PbScTaO).
In re claim 12, Shen et al. shows (figs. 2, 3, 4) wherein each of the semiconductor pattern comprises at least one of a Si-based semiconductor material, a two- dimensional (2D) semiconductor material, and an oxide semiconductor material.
(Translation portion)
The plurality of semiconductor pattern APs may be formed of, for example, undoped semiconductor material or doped semiconductor material. In one embodiment, a plurality of semiconductor pattern AP can be formed by polysilicon. In one embodiment, a plurality of semiconductor pattern AP may include an amorphous metal oxide, polycrystalline metal oxide or a combination thereof, such as In-Ga-based oxide (IGO), In-Zn-based oxide (IZO) or In-Ga-Zn-based oxide (IGZO). In one embodiment, a plurality of semiconductor pattern AP may include a 2 D material semiconductor. In one embodiment, the 2D material semiconductor may include MoS2, WSe2, graphene, carbon nano-tube or a combination thereof. As used herein, the term "or" is not exclusive term, for example, "A or B" will include A, B, or A and B.
In re claim 13, Shen et al. shows (figs. 2, 3, 4, 5) a three-dimensional (3D) ferroelectric random access memory (FeRAM) comprising: a substrate (110); semiconductor patterns (AP) stacked in a vertical direction (Z) on the substrate in a multilayer structure with insulating layers (IL) therebetween, and spaced apart from each other in a first horizontal direction (Y); bit lines (BL) on first side surfaces of the semiconductor patterns in a second horizontal direction (X), wherein the second horizontal direction is perpendicular to the first horizontal direction, and the bit lines extend in the first horizontal direction (Y) and are spaced apart from each other in the vertical direction (Z); first electrodes (LE) on second side surfaces of the semiconductor patterns in the second horizontal direction, wherein the first electrodes are spaced apart from each other in both the vertical direction and the first horizontal direction, and each of the first electrodes has a ‘ Է ' shape on each of a horizontal cross-section perpendicular to the vertical direction and a vertical cross-section perpendicular to the first horizontal direction; a ferroelectric layer (DL) on the first electrodes in the second horizontal direction, wherein the ferroelectric layer extends in the first horizontal direction, and comprises a ‘ Է ' shaped portion along each of the horizontal cross-section and the vertical cross-section, in correspondence to the ‘ Է ' shape of each of the first electrodes; second electrodes (UE) on the ferroelectric layer in the second horizontal direction, wherein the second electrodes extend in the first horizontal direction (Y) are spaced apart from each other in the vertical direction (Z), and each of the second electrodes has a rectangular shape filling a ‘ Է ' shaped inside of the ferroelectric layer on the vertical cross-section; and word lines (WL) between two adjacent semiconductor patterns among the semiconductor patterns in the first horizontal direction, wherein the word lines extend in the vertical direction.
In re claim 14, Shen et al. shows (figs. 2, 3, 4) wherein each of the second electrodes (UE) comprises: an extension extending in the first horizontal direction (Y) on the horizontal cross-section; and a protrusion protruding in the second horizontal direction (X) from the extension in correspondence to the ‘ Է ' shape of the ferroelectric layer on the horizontal cross-section.
In re claim 16, Shen et al. shows (figs. 2, 3, 4) a three-dimensional (3D) ferroelectric random access memory (FeRAM) comprising: a substrate (110); semiconductor patterns (AP) stacked in a vertical direction (Z) on the substrate in a multilayer structure with insulating layers (IL) therebetween, and spaced apart from each other in a first horizontal direction (Y); bit lines (BL) on first side surface of the semiconductor patterns in a second horizontal direction (X), wherein the second horizontal direction is perpendicular to the first horizontal direction, and the bit lines extend in the first horizontal direction and are spaced apart from each other in the vertical direction (Z); first electrodes (LE) on second side surfaces of the semiconductor patterns in the second horizontal direction (X), wherein the first electrodes are spaced apart from each other in both the vertical direction (Z) and the first horizontal direction (Y), wherein each of a horizontal cross-section perpendicular to the vertical direction and a vertical cross-section perpendicular to the first horizontal direction has a rectangular shape; ferroelectric layers (DL) on the first electrodes in the second horizontal direction, wherein the ferroelectric layers in the first horizontal direction, are spaced apart from each other in the vertical direction, and have a ‘ Է ' shape on the vertical cross-section; second electrodes (UE) on the ferroelectric layers in the second horizontal direction, wherein the second electrodes extend in the first horizontal direction (Y), are spaced apart from each other in the vertical direction (Z), and each has a rectangular shape filling a ‘ Է ' -shaped inside of each of the ferroelectric layers on the vertical cross-section; and word lines (WL) between two adjacent semiconductor patterns among the semiconductor patterns in the first horizontal direction (Y), wherein the word lines extend in the vertical direction (Z).
In re claim 17, Shen et al. shows (figs. 2, 3, 4) wherein each of the ferroelectric layers comprises: an extension extending in the first horizontal direction; and a protrusion protruding in the second horizontal direction from the extension and contacting each of the first electrodes, and wherein the extension and the protrusion form a 'T' shape in correspondence to one of the semiconductor patterns.
In re claim 18, Shen et al. shows (figs. 2, 3, 4) wherein each of the second electrodes (UE) has a straight band shape extending in the first horizontal direction (Y) on the horizontal cross-section.
In re claim 19, Shen et al. shows (figs. 2, 3, 4) wherein each of the bit lines (BL) has a straight band shape extending in the first horizontal direction (Y).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been ovious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 11 are rejected under 35 U.S.C. 103 as being unpatentable over Shen et al. (CN114171520A) as applied to claim 1 above, and further in view of the cited case law.
In re claim 11, Shen does not disclose wherein the ferroelectric layer has a multilayer structure comprising at least two different material films. However, it would have been obvious to one of ordinary skill in the art to use three, four, etc., ferroelectic layers since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960). See also MPEP 2144.04 VI. (B).
Allowable Subject Matter
Claims 5 and 15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Park (US Pub. 2023/0019055 A1), Kim (US 11,844,206 B2), He (US 12,178,038 B2), Lee (US Pub. 2019/0164985 A1), Shin (US Pub. 2020/0411523 A1), Ryu (CN 114373801 A), and Jung (KR-20220017774 A) also disclose various elements of the claims.
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/MATTHEW E WARREN/Primary Examiner, Art Unit 2817
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