DETAILED ACTION
Election/Restrictions
Applicant's election with traverse of Group I and Species 1 in the reply filed on 5/19/26 is acknowledged. The traversal is on the ground(s) that figures 9A-c and 10A-B teach processes, not the elected products. This is not found persuasive because the resultant products (shown in figures 9C & 10B) of each group are patentably distinct substrates.
The requirement is still deemed proper and is therefore made FINAL.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 12 and 13 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 12 and 13 recite “a second integrated device” on a third substrate, but claim 10 recites “a second integrated device” on the second substrate. This duplicate language is confusing. For examination purposes it will be assumed that claims 12 and 13 intended to claim “a third integrated device”.
Rejection over Lee et al., US 2004/0038740
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-8, and 10-11 is/are rejected under 35 U.S.C. 102(a)(2) as being clearly anticipated by Lee et al., US 2004/0038740.
Regarding claim 1, Lee (figure 1) teaches a package comprising:
a first substrate 300 comprising:
at least one first dielectric layer 310; and
a first plurality of interconnects 330, wherein the first plurality of interconnects include a first plurality of post interconnects 210;
a first integrated device 112 coupled (using 130) to the first substrate 300;
a second substrate 400 coupled to the first substrate 300 through at least a plurality of solder interconnects 230, wherein the second substrate 400 comprises:
at least one second dielectric layer 410; and
a second plurality of interconnects 430, wherein the second plurality of interconnects 430 include a second plurality of post interconnects 220; and
an encapsulation layer 250 located between the first substrate 300 and the second substrate 400.
With respect to claim 2, Lee (figure 1) teaches the encapsulation layer 250 touches the first substrate 300, the second substrate 400, the plurality of solder interconnects 230 and the first integrated device 112.
As to claim 3, Lee (figure 1) teaches the encapsulation layer 250 is located between the second substrate 400 and the first integrated device 112.
In re claim 4, Lee (figure 1) teaches the encapsulation layer 250 touches the second substrate 400 and a back side of the first integrated device 112.
Concerning claim 5, Lee (figure 1) teaches the plurality of solder interconnects 230 are coupled to the first plurality of post interconnects 210 and the second plurality of post interconnects 220.
Pertaining to claim 6, Lee (figure 1) teaches the encapsulation layer 250 touches the plurality of solder interconnects 230.
In claim 7, Lee (figure 1) teaches the encapsulation layer 250 further touches the first integrated device 112.
Regarding claim 8, Lee (figure 1) teaches the first integrated device 112 is coupled to the first substrate 300 through a second plurality of solder (paragraph 0029) interconnects 130.
With respect to claim 10, Lee (figure 11) teaches a second integrated device 912 coupled to the second substrate 400 through a second plurality of solder interconnects 950.
As to claim 11, wherein an electrical path between the first integrated device 112 and the second integrated device 912 comprises an interconnect from the first plurality of interconnects 330, a post interconnect 910 from the first plurality of post interconnects 210, a solder interconnect 230 from the plurality of solder interconnects 230, a post interconnect 220 from the second plurality of post interconnects 220, an interconnect 430 from the second plurality of post interconnects, and a solder interconnect 950 from the second plurality of solder interconnects 950.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 9, 12 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al., US 2004/0038740 as applied to claim 1 above.
In re claim 9, though Lee (figure 1) teaches the first integrated device 112 is coupled to the first substrate 300 a second plurality of solder interconnects 130, and though Lee fails to teach also using a plurality of pillar interconnects it would have been obvious to one of ordinary skill in the art at the time of the invention to also use a plurality of pillar interconnects in the invention of Lee because this combination of interconnects is a known equivalent interconnection combination. The substitution of one known equivalent technique for another may be obvious even if the prior art does not expressly suggest the substitution (Ex parte Novak 16 USPQ 2d 2041 (BPAI 1989); In re Mostovych 144 USPQ 38 (CCPA 1964); In re Leshin 125 USPQ 416 (CCPA 1960); Graver Tank & Manufacturing Co. V. Linde Air Products Co. 85 USPQ 328 (USSC 1950).
Concerning claim 12, though Lee fails to teach a third substrate coupled to the second substrate through a second plurality of solder interconnects, wherein the third substrate comprises: at least one third dielectric layer; and a third plurality of interconnects; and a second integrated device coupled to the third substrate through a third plurality of solder interconnects, it would have been obvious to one of ordinary skill in the art at the time of the invention to use a third substrate and a second integrated device in the invention of Lee because the mere duplication of parts has no patentable significance unless a new and unexpected result is produced (In re Harza, 124 USPQ 378 (CCPA 1960)). Creating a plurality of integrated devices on substrate stacks is well known to skilled artisans.
Pertaining to claim 13, though Lee fails to teach an electrical path between the first integrated device 112 and the second (sic third) integrated device comprises an interconnect from the first plurality of interconnects 330, a post interconnect 210 from the first plurality of post interconnects 210, a solder interconnect 230 from the plurality of solder interconnects 230, a post interconnect 220 from the second plurality of post interconnects 220, an interconnect 430 from the second plurality of post interconnects 430, a solder interconnect 950 from the second plurality of solder interconnects 950 , an interconnect from the third plurality of interconnects, and a solder interconnect from the third plurality of solder interconnects, it would have been obvious to one of ordinary skill in the art at the time of the invention to use this electrical path in the invention of Lee because it is conventionally known and used in the art and taught in relation to the first integrated device 112 and the second integrated device 912. The use of conventional materials to perform their known functions is obvious (MPEP 2144.07).
Rejection over Wu et al., US 5016/0056087
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-11 is/are rejected under 35 U.S.C. 102a1 as being clearly anticipated by Wu et al., US 5016/0056087.
In claim 1, Wu (figure 5) teaches a package comprising:
a first substrate 110 comprising:
at least one first dielectric layer (paragraph 0015); and
a first plurality of interconnects 112/106, wherein the first plurality of interconnects 112/106/202 include a first plurality of post interconnects 202;
a first integrated device 302 coupled to the first substrate 110;
a second substrate 402 coupled to the first substrate 110 through at least a plurality of solder interconnects 414, wherein the second substrate 402 comprises:
at least one second dielectric layer 408; and
a second plurality of interconnects 410/416, wherein the second plurality of interconnects 410 include a second plurality of post interconnects 416; and
an encapsulation layer 502 located between the first substrate 110 and the second substrate 402.
Regarding claim 2, Wu (figure 5) teaches the encapsulation layer 502 touches the first substrate, the second substrate, the plurality of solder interconnects and the first integrated device.
With respect to claim 3, Wu (figure 5) teaches the encapsulation layer 502 is located between the second substrate 402 and the first integrated device 302.
As to claim 4, Wu (figure 5) teaches the encapsulation layer 502 touches the second substrate 402 and a back side of the first integrated device 302.
In re claim 5, Wu (figure 5) teaches the plurality of solder interconnects 414 are coupled to the first plurality of post interconnects 202 and the second plurality of post interconnects 416.
Concerning claim 6, Wu (figure 5) teaches the encapsulation layer 502 touches the plurality of solder interconnects 414.
Pertaining to claim 7. The package of claim 5, Wu (figure 5) teaches the encapsulation layer 502 further touches the first integrated device 302.
In claim 8, Wu (figure 3) teaches the first integrated device 302 is coupled to the first substrate 110 through a second plurality of solder interconnects 304.
Regarding claim 9, Wu (figure 3 & paragraph 0020) teaches the first integrated device 302 is coupled to the first substrate 110 through a plurality of pillar interconnects 304 and a second plurality of solder interconnects 304.
With respect to claim 10, Wu (figure 7) teaches a second integrated device 710 coupled to the second substrate 402 through a second plurality of solder interconnects 704. The comprising language of the claim allows for the extra components.
As to claim 11, Wu (figure 5) teaches an electrical path between the first integrated device 302 and the second integrated device 710 comprises an interconnect 112/106 from the first plurality of interconnects 112/106, a post interconnect 202 from the first plurality of post interconnects 202, a solder interconnect 414 from the plurality of solder interconnects 414, a post interconnect 416 from the second plurality of post interconnects 416, an interconnect 410 from the second plurality of post interconnects 410, and a solder interconnect 704 from the second plurality of solder interconnects 704.
Claim(s) 12 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al., US 5016/0056087, as applied to claim 1 above.
In re claim 12, though Wu fails to teach a third substrate coupled to the second substrate through a second plurality of solder interconnects, wherein the third substrate comprises: at least one third dielectric layer; and a third plurality of interconnects; and a second integrated device coupled to the third substrate through a third plurality of solder interconnects, , it would have been obvious to one of ordinary skill in the art at the time of the invention to use a third substrate and a second integrated device in the invention of Lee because the mere duplication of parts has no patentable significance unless a new and unexpected result is produced (In re Harza, 124 USPQ 378 (CCPA 1960)). Creating a plurality of integrated devices on substrate stacks is well known to skilled artisans.
Concerning claim 13, though Wu fails to teach an electrical path between the first integrated device and the second integrated device comprises an interconnect from the first plurality of interconnects, a post interconnect from the first plurality of post interconnects, a solder interconnect from the plurality of solder interconnects, a post interconnect from the second plurality of post interconnects, an interconnect from the second plurality of post interconnects, a solder interconnect from the second plurality of solder interconnects, an interconnect from the third plurality of interconnects, and a solder interconnect from the third plurality of solder interconnects, it would have been obvious to one of ordinary skill in the art at the time of the invention to use this electrical path in the invention of Lee because it is conventionally known and used in the art and taught in relation to the first integrated device 112 and the second integrated device 912. The use of conventional materials to perform their known functions is obvious (MPEP 2144.07).
Rejection over Kim et al., US 2015/0221601
Claim(s) 1-8 is/are rejected under 35 U.S.C. 102a1 as being clearly anticipated by Kim et al., US 2015/0221601.
Pertaining to claim 1, Kim (figure 1N) teaches a package comprising:
a first substrate 110 comprising:
at least one first dielectric layer 111; and
a first plurality of interconnects 112, wherein the first plurality of interconnects 112 include a first plurality of post interconnects 114;
a first integrated device 130 coupled to the first substrate 110;
a second substrate 120 coupled to the first substrate 110 through at least a plurality of solder interconnects 114a/124a, wherein the second substrate 120 comprises:
at least one second dielectric layer 121; and
a second plurality of interconnects 122, wherein the second plurality of interconnects 122 include a second plurality of post interconnects 124; and
an encapsulation layer 150 located between the first substrate 110 and the second substrate 120.
In claim 2, Kim (figure 1N) teaches the encapsulation layer 150 touches the first substrate 110, the second substrate 120, the plurality of solder interconnects 114a/124a and the first integrated device 130.
Regarding claim 3, Kim (figure 1N) teaches the encapsulation layer 150 is located between the second substrate 120 and the first integrated device 130.
With respect to claim 4, Kim (figure 1N) teaches the encapsulation layer 150 touches the second substrate 120 and a back side of the first integrated device 130.
As to claim 5, Kim (figure 1N) teaches the plurality of solder interconnects 114a/124a are coupled to the first plurality of post interconnects 114 and the second plurality of post interconnects 124.
In re claim 6, Kim (figure 1N) teaches the encapsulation layer 150 touches the plurality of solder interconnects 114a/124a.
Concerning claim 7, Kim (figure 1N) teaches the encapsulation layer 150 further touches the first integrated device 130.
Pertaining to claim 8, Kim (figure 1N) teaches the first integrated device 130 is coupled to the first substrate 110 through a second plurality of solder interconnects 113a.
Claim(s) 9-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al., US 2015/0221601, as applied to claim 1 above.
In claim 9, Kim (figure 1N) teaches the first integrated device 130 is coupled to the first substrate 110 through a second plurality of solder interconnects 113a, and though Kim fails to teach also using a plurality of pillar interconnects 113, it would have been obvious to one of ordinary skill in the art at the time of the invention to also use a plurality of pillar interconnects in the invention of Lee because this combination of interconnects is a known equivalent interconnection combination. The substitution of one known equivalent technique for another may be obvious even if the prior art does not expressly suggest the substitution (Ex parte Novak 16 USPQ 2d 2041 (BPAI 1989); In re Mostovych 144 USPQ 38 (CCPA 1964); In re Leshin 125 USPQ 416 (CCPA 1960); Graver Tank & Manufacturing Co. V. Linde Air Products Co. 85 USPQ 328 (USSC 1950).
Regarding claim 10, Kim (figure 8) teaches a second integrated device (top 130) coupled to the second substrate 120, and though Kim fails to specifically teach using a second plurality of solder interconnects, it would have been obvious to one of ordinary skill in the art at the time of the invention to use solder interconnects in the invention of Kim because solder interconnects are conventionally known and used interconnects. The use of conventional materials to perform their known functions is obvious (MPEP 2144.07).
With respect to claim 11, Kim (figure 8) teaches an electrical path between the first integrated device 130 and the second integrated device (top 130) comprises an interconnect 112 from the first plurality of interconnects 112, a post interconnect 114 from the first plurality of post interconnects 114, a solder interconnect 114a/124a from the plurality of solder interconnects 114a/124a, a post interconnect 124 from the second plurality of post interconnects 124, an interconnect (top 112) from the second plurality of post interconnects (top 112), and a interconnect (connection between (bottom 100 & top 100) from the second plurality of interconnects (connection between bottom 100 &top 100). Though Kim fails to teach the second plurality of interconnects are made of solder, it would have been obvious to one of ordinary skill in the art at the time of the invention to use the solder in the invention of Kim because solder is a conventionally known and used interconnect. The use of conventional materials to perform their known functions is obvious (MPEP 2144.07).
As to claim 12, though Kim fails to teach a third substrate coupled to the second substrate through a second plurality of solder interconnects, wherein the third substrate comprises: at least one third dielectric layer; and a third plurality of interconnects; and a second integrated device coupled to the third substrate through a third plurality of solder interconnects, it would have been obvious to one of ordinary skill in the art at the time of the invention to use a third substrate and integrated device in the invention of Kim because the mere duplication of parts has no patentable significance unless a new and unexpected result is produced (In re Harza, 124 USPQ 378 (CCPA 1960)).
In re claim 13, though Kim fails to teach an electrical path between the first integrated device and the second integrated device comprises an interconnect from the first plurality of interconnects, a post interconnect from the first plurality of post interconnects, a solder interconnect from the plurality of solder interconnects, a post interconnect from the second plurality of post interconnects, an interconnect from the second plurality of post interconnects, a solder interconnect from the second plurality of solder interconnects, an interconnect from the third plurality of interconnects, and a solder interconnect from the third plurality of solder interconnects, it would have been obvious to one of ordinary skill in the art at the time of the invention to use this electrical path in the invention of Lee because it is conventionally known and used in the art and taught in relation to the first integrated device 112 and the second integrated device 912. The use of conventional materials to perform their known functions is obvious (MPEP 2144.07).
Rejection over Yamano et al., US 7,989,707
Claim(s) 1-8 is/are rejected under 35 U.S.C. 102a1 as being clearly anticipated by Yamano et al., US 7,989,707.
Concerning claim 1, Yamano (figure 13) teaches a package comprising:
a first substrate 101 comprising:
at least one first dielectric layer 101; and
a first plurality of interconnects 102, wherein the first plurality of interconnects 102 include a first plurality of post interconnects PS3;
a first integrated device 10 coupled to the first substrate 101;
a second substrate 201 coupled to the first substrate 101 through at least a plurality of solder interconnects AD3, wherein the second substrate 201 comprises:
at least one second dielectric layer 201; and
a second plurality of interconnects 202, wherein the second plurality of interconnects 202 include a second plurality of post interconnects PS4; and
an encapsulation layer D1 located between the first substrate 101 and the second substrate 201.
Pertaining to claim 2, Yamano (figure 13) teaches the encapsulation layer D1 touches the first substrate 101, the second substrate 201, the plurality of solder interconnects AD3 and the first integrated device 10.
In claim 3, Yamano (figure 13) teaches the encapsulation layer D1 is located between the second substrate 201 and the first integrated device 10.
Regarding claim 4, Yamano (figure 13) teaches the encapsulation layer D1 touches the second substrate 201 and a back side of the first integrated device 10.
With respect to claim 5, Yamano (figure 13) teaches the plurality of solder interconnects AD3 are coupled to the first plurality of post interconnects PS3 and the second plurality of post interconnects PS4.
As to claim 6, Yamano (figure 13) teaches the encapsulation layer D1 touches the plurality of solder interconnects AD3.
In re claim 7, Yamano (figure 13) teaches the encapsulation layer D1 further touches the first integrated device 10.
Concerning claim 8, Yamano (figure 13) teaches the first integrated device 10 is coupled to the first substrate 101 through a second plurality of solder interconnects 107.
Claim(s) 9-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yamano et al., US 7,989,707, as applied to claim 1 above.
Pertaining to claim 9, though Yamano fails to teach the first integrated device 10 is coupled to the first substrate through a plurality of pillar interconnects and a second plurality of solder interconnects, it would have been obvious to one of ordinary skill in the art at the time of the invention to use this interconnect in place of the one in the invention of Yamano because they are known equivalent interconnects. The substitution of one known equivalent technique for another may be obvious even if the prior art does not expressly suggest the substitution (Ex parte Novak 16 USPQ 2d 2041 (BPAI 1989); In re Mostovych 144 USPQ 38 (CCPA 1964); In re Leshin 125 USPQ 416 (CCPA 1960); Graver Tank & Manufacturing Co. V. Linde Air Products Co. 85 USPQ 328 (USSC 1950).
In claim 10, Yamano (figure 31) teaches a second integrated device EL3 coupled to the second substrate 200 through a second plurality of interconnects (between EL3 & 200), and though Yamano fails to teach the interconnects are made of solder, it would have been obvious to one of ordinary skill in the art at the time of the invention to use solder in the invention of Yamano solder is a conventionally known and used interconnect. The use of conventional materials to perform their known functions is obvious (MPEP 2144.07).
Regarding claim 11, Yamano (figure 31 & 13) teaches an electrical path between the first integrated device 110 and the second integrated device EL3 comprises an interconnect 102b/103A from the first plurality of interconnects 102b/103A, a post interconnect PS3 from the first plurality of post interconnects PS3, a solder interconnect AD3 from the plurality of solder interconnects AD3, a post interconnect PS4 from the second plurality of post interconnects PS4, an interconnect 202 from the second plurality of post interconnects 202, and a solder interconnect (between EL3 & 200) from the second plurality of solder interconnects (between EL3 & 200).
With respect to claim 12, though Yamano fails to teach a third substrate coupled to the second substrate through a second plurality of solder interconnects, wherein the third substrate comprises: at least one third dielectric layer; and a third plurality of interconnects; and a second integrated device coupled to the third substrate through a third plurality of solder interconnects, it would have been obvious to one of ordinary skill in the art at the time of the invention to use a third substrate and integrated device in the invention of Yamano because the mere duplication of parts has no patentable significance unless a new and unexpected result is produced (In re Harza, 124 USPQ 378 (CCPA 1960)).
As to claim 13, though Yamano fails to teach an electrical path between the first integrated device and the second integrated device comprises an interconnect from the first plurality of interconnects, a post interconnect from the first plurality of post interconnects, a solder interconnect from the plurality of solder interconnects, a post interconnect from the second plurality of post interconnects, an interconnect from the second plurality of post interconnects, a solder interconnect from the second plurality of solder interconnects, an interconnect from the third plurality of interconnects, and a solder interconnect from the third plurality of solder interconnects, it would have been obvious to one of ordinary skill in the art at the time of the invention to use this electrical path in the invention of Yamano because the mere duplication of parts has no patentable significance unless a new and unexpected result is produced (In re Harza, 124 USPQ 378 (CCPA 1960)).
Conclusion
Any inquiry should be directed to DAVID A ZARNEKE at (571)272-1937. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matt Landau can be reached at 571-272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DAVID A ZARNEKE/Primary Examiner, Art Unit 2891 6/30/26
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